From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 8473A386FC28; Tue, 8 Jun 2021 16:49:56 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 8473A386FC28 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work055)] Add IEEE 128-bit min/max support on PowerPC. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work055 X-Git-Oldrev: b63884e5925d2ac604b339b84ebef6d8d95d2759 X-Git-Newrev: ad3a024c9cfdb64e20c0e3fac5bd54a1b25b9528 Message-Id: <20210608164956.8473A386FC28@sourceware.org> Date: Tue, 8 Jun 2021 16:49:56 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 08 Jun 2021 16:49:56 -0000 https://gcc.gnu.org/g:ad3a024c9cfdb64e20c0e3fac5bd54a1b25b9528 commit ad3a024c9cfdb64e20c0e3fac5bd54a1b25b9528 Author: Michael Meissner Date: Tue Jun 8 12:49:34 2021 -0400 Add IEEE 128-bit min/max support on PowerPC. This patch adds the support for the IEEE 128-bit floating point C minimum and maximum instructions. The next patch will add the support for using the compare and set mask instruction to implement conditional moves. This patch does not try to re-use the code used for SF/DF min/max support. It defines a separate insn for the IEEE 128-bit support. It uses the code iterator to simplify adding both operations. GCC will not convert ternary operations into using min/max instructions provided in this patch unless the user uses -Ofast or similar switches due to issues with NaNs. The next patch that adds conditional move instructions will enable the ternary conversion in many cases. The float128-minmax.c test generates the xsmincqp and xsmaxcqp instructions on power10. This patch adjusts the test to accomidate this. gcc/ 2021-06-08 Michael Meissner * config/rs6000/rs6000.c (rs6000_emit_minmax): Add support for ISA 3.1 IEEE 128-bit floating point xsmaxcqp and xsmincqp instructions. * config/rs6000/rs6000.md (s3, IEEE128 iterator): New insns. gcc/testsuite/ 2021-06-08 Michael Meissner * gcc.target/powerpc/float128-minmax-2.c: New test. * gcc.target/powerpc/float128-minmax.c: Adjust expected code for power10. * lib/target-supports.exp (check_effective_target_has_arch_pwr10): New target support. Diff: --- gcc/config/rs6000/rs6000.c | 3 ++- gcc/config/rs6000/rs6000.md | 11 +++++++++++ gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c | 15 +++++++++++++++ gcc/testsuite/gcc.target/powerpc/float128-minmax.c | 8 +++++--- gcc/testsuite/lib/target-supports.exp | 10 ++++++++++ 5 files changed, 43 insertions(+), 4 deletions(-) diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index b01bb5c8191..1651788df6a 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -16103,7 +16103,8 @@ rs6000_emit_minmax (rtx dest, enum rtx_code code, rtx op0, rtx op1) /* VSX/altivec have direct min/max insns. */ if ((code == SMAX || code == SMIN) && (VECTOR_UNIT_ALTIVEC_OR_VSX_P (mode) - || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)))) + || (mode == SFmode && VECTOR_UNIT_VSX_P (DFmode)) + || (TARGET_POWER10 && TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)))) { emit_insn (gen_rtx_SET (dest, gen_rtx_fmt_ee (code, mode, op0, op1))); return; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3f59b544f6a..064c3a2d9d6 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -5214,6 +5214,17 @@ } [(set_attr "type" "fp")]) +;; Min/max for ISA 3.1 IEEE 128-bit floating point +(define_insn "s3" + [(set (match_operand:IEEE128 0 "altivec_register_operand" "=v") + (fp_minmax:IEEE128 + (match_operand:IEEE128 1 "altivec_register_operand" "v") + (match_operand:IEEE128 2 "altivec_register_operand" "v")))] + "TARGET_POWER10" + "xscqp %0,%1,%2" + [(set_attr "type" "vecfloat") + (set_attr "size" "128")]) + ;; The conditional move instructions allow us to perform max and min operations ;; even when we don't have the appropriate max/min instruction using the FSEL ;; instruction. diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c new file mode 100644 index 00000000000..c71ba08c9f8 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax-2.c @@ -0,0 +1,15 @@ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ffast-math" } */ + +#ifndef TYPE +#define TYPE _Float128 +#endif + +/* Test that the fminf128/fmaxf128 functions generate if/then/else and not a + call. */ +TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); } +TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); } + +/* { dg-final { scan-assembler {\mxsmaxcqp\M} } } */ +/* { dg-final { scan-assembler {\mxsmincqp\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c index fe397518f2f..efb4ce232f9 100644 --- a/gcc/testsuite/gcc.target/powerpc/float128-minmax.c +++ b/gcc/testsuite/gcc.target/powerpc/float128-minmax.c @@ -1,6 +1,5 @@ -/* { dg-do compile { target lp64 } } */ /* { dg-require-effective-target powerpc_p9vector_ok } */ -/* { dg-require-effective-target float128 } */ +/* { dg-require-effective-target powerpc_float128_hw } */ /* { dg-options "-mpower9-vector -O2 -ffast-math" } */ #ifndef TYPE @@ -12,5 +11,8 @@ TYPE f128_min (TYPE a, TYPE b) { return __builtin_fminf128 (a, b); } TYPE f128_max (TYPE a, TYPE b) { return __builtin_fmaxf128 (a, b); } -/* { dg-final { scan-assembler {\mxscmpuqp\M} } } */ +/* Adjust code power10 which has native min/max instructions. */ +/* { dg-final { scan-assembler {\mxscmpuqp\M} } { target { ! has_arch_pwr10 } } } */ +/* { dg-final { scan-assembler {\mxsmincqp\M} } { target { has_arch_pwr10 } } } */ +/* { dg-final { scan-assembler {\mxsmaxcqp\M} } { target { has_arch_pwr10 } } } */ /* { dg-final { scan-assembler-not {\mbl\M} } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/target-supports.exp index 7f78c5593ac..789723fb287 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -6127,6 +6127,16 @@ proc check_effective_target_has_arch_pwr9 { } { }] } +proc check_effective_target_has_arch_pwr10 { } { + return [check_no_compiler_messages arch_pwr10 assembly { + #ifndef _ARCH_PWR10 + #error does not have power10 support. + #else + /* "has power10 support" */ + #endif + }] +} + # Return 1 if this is a PowerPC target supporting -mcpu=power10. # Limit this to 64-bit linux systems for now until other targets support # power10.