From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7835) id 9B2D9383D811; Wed, 16 Jun 2021 13:23:15 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 9B2D9383D811 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jonathan Wright To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-1530] testsuite: aarch64: Add zero-high-half tests for narrowing shifts X-Act-Checkin: gcc X-Git-Author: Jonathan Wright X-Git-Refname: refs/heads/master X-Git-Oldrev: d7deee423f993bee8ee440f6fe0c9126c316c64b X-Git-Newrev: ac6c858d072016ad2c409f1593fa290ad0d87e11 Message-Id: <20210616132315.9B2D9383D811@sourceware.org> Date: Wed, 16 Jun 2021 13:23:15 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Jun 2021 13:23:15 -0000 https://gcc.gnu.org/g:ac6c858d072016ad2c409f1593fa290ad0d87e11 commit r12-1530-gac6c858d072016ad2c409f1593fa290ad0d87e11 Author: Jonathan Wright Date: Tue Jun 15 15:03:09 2021 +0100 testsuite: aarch64: Add zero-high-half tests for narrowing shifts Add tests to verify that Neon narrowing-shift instructions clear the top half of the result vector. It is sufficient to show that a subsequent combine with a zero-vector is optimized away - leaving just the narrowing-shift instruction. gcc/testsuite/ChangeLog: 2021-06-15 Jonathan Wright * gcc.target/aarch64/narrow_zero_high_half.c: New test. Diff: --- .../gcc.target/aarch64/narrow_zero_high_half.c | 60 ++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c b/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c new file mode 100644 index 00000000000..a79a4c33dab --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/narrow_zero_high_half.c @@ -0,0 +1,60 @@ +/* { dg-skip-if "" { arm*-*-* } } */ +/* { dg-do compile } */ +/* { dg-options "-O3" } */ + +#include + +#define TEST_SHIFT(name, rettype, intype, fs, rs) \ + rettype test_ ## name ## _ ## fs ## _zero_high \ + (intype a) \ + { \ + return vcombine_ ## rs (name ## _ ## fs (a, 4), \ + vdup_n_ ## rs (0)); \ + } + +TEST_SHIFT (vshrn_n, int8x16_t, int16x8_t, s16, s8) +TEST_SHIFT (vshrn_n, int16x8_t, int32x4_t, s32, s16) +TEST_SHIFT (vshrn_n, int32x4_t, int64x2_t, s64, s32) +TEST_SHIFT (vshrn_n, uint8x16_t, uint16x8_t, u16, u8) +TEST_SHIFT (vshrn_n, uint16x8_t, uint32x4_t, u32, u16) +TEST_SHIFT (vshrn_n, uint32x4_t, uint64x2_t, u64, u32) + +TEST_SHIFT (vrshrn_n, int8x16_t, int16x8_t, s16, s8) +TEST_SHIFT (vrshrn_n, int16x8_t, int32x4_t, s32, s16) +TEST_SHIFT (vrshrn_n, int32x4_t, int64x2_t, s64, s32) +TEST_SHIFT (vrshrn_n, uint8x16_t, uint16x8_t, u16, u8) +TEST_SHIFT (vrshrn_n, uint16x8_t, uint32x4_t, u32, u16) +TEST_SHIFT (vrshrn_n, uint32x4_t, uint64x2_t, u64, u32) + +TEST_SHIFT (vqshrn_n, int8x16_t, int16x8_t, s16, s8) +TEST_SHIFT (vqshrn_n, int16x8_t, int32x4_t, s32, s16) +TEST_SHIFT (vqshrn_n, int32x4_t, int64x2_t, s64, s32) +TEST_SHIFT (vqshrn_n, uint8x16_t, uint16x8_t, u16, u8) +TEST_SHIFT (vqshrn_n, uint16x8_t, uint32x4_t, u32, u16) +TEST_SHIFT (vqshrn_n, uint32x4_t, uint64x2_t, u64, u32) + +TEST_SHIFT (vqrshrn_n, int8x16_t, int16x8_t, s16, s8) +TEST_SHIFT (vqrshrn_n, int16x8_t, int32x4_t, s32, s16) +TEST_SHIFT (vqrshrn_n, int32x4_t, int64x2_t, s64, s32) +TEST_SHIFT (vqrshrn_n, uint8x16_t, uint16x8_t, u16, u8) +TEST_SHIFT (vqrshrn_n, uint16x8_t, uint32x4_t, u32, u16) +TEST_SHIFT (vqrshrn_n, uint32x4_t, uint64x2_t, u64, u32) + +TEST_SHIFT (vqshrun_n, uint8x16_t, int16x8_t, s16, u8) +TEST_SHIFT (vqshrun_n, uint16x8_t, int32x4_t, s32, u16) +TEST_SHIFT (vqshrun_n, uint32x4_t, int64x2_t, s64, u32) + +TEST_SHIFT (vqrshrun_n, uint8x16_t, int16x8_t, s16, u8) +TEST_SHIFT (vqrshrun_n, uint16x8_t, int32x4_t, s32, u16) +TEST_SHIFT (vqrshrun_n, uint32x4_t, int64x2_t, s64, u32) + +/* { dg-final { scan-assembler-not "dup\\t" } } */ + +/* { dg-final { scan-assembler-times "\\tshrn\\tv" 6} } */ +/* { dg-final { scan-assembler-times "\\trshrn\\tv" 6} } */ +/* { dg-final { scan-assembler-times "\\tsqshrn\\tv" 3} } */ +/* { dg-final { scan-assembler-times "\\tuqshrn\\tv" 3} } */ +/* { dg-final { scan-assembler-times "\\tsqrshrn\\tv" 3} } */ +/* { dg-final { scan-assembler-times "\\tuqrshrn\\tv" 3} } */ +/* { dg-final { scan-assembler-times "\\tsqshrun\\tv" 3} } */ +/* { dg-final { scan-assembler-times "\\tsqrshrun\\tv" 3} } */