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From: Uros Bizjak <uros@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-1743] i386: Prevent unwanted combine from LZCNT to BSR [PR101175] Date: Wed, 23 Jun 2021 10:51:44 +0000 (GMT) [thread overview] Message-ID: <20210623105144.4D3A3386101E@sourceware.org> (raw) https://gcc.gnu.org/g:1e16f2b472c7d253d564556a048dc4ae16119c00 commit r12-1743-g1e16f2b472c7d253d564556a048dc4ae16119c00 Author: Uros Bizjak <ubizjak@gmail.com> Date: Wed Jun 23 12:50:53 2021 +0200 i386: Prevent unwanted combine from LZCNT to BSR [PR101175] The current RTX pattern for BSR allows combine pass to convert LZCNT insn to BSR. Note that the LZCNT has a defined behavior to return the operand size when operand is zero, where BSR has not. Add a BSR specific setting of zero-flag to RTX pattern of BSR insn in order to avoid matching unwanted combinations. 2021-06-23 Uroš Bizjak <ubizjak@gmail.com> gcc/ PR target/101175 * config/i386/i386.md (bsr_rex64): Add zero-flag setting RTX. (bsr): Ditto. (*bsrhi): Remove. (clz<mode>2): Update RTX pattern for additions. gcc/testsuite/ PR target/101175 * gcc.target/i386/pr101175.c: New test. Diff: --- gcc/config/i386/i386.md | 36 +++++++++++++------------------- gcc/testsuite/gcc.target/i386/pr101175.c | 28 +++++++++++++++++++++++++ 2 files changed, 43 insertions(+), 21 deletions(-) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 700c158a432..4e242105719 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -14533,10 +14533,12 @@ (set_attr "mode" "SI")]) (define_insn "bsr_rex64" - [(set (match_operand:DI 0 "register_operand" "=r") + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ (match_operand:DI 1 "nonimmediate_operand" "rm") + (const_int 0))) + (set (match_operand:DI 0 "register_operand" "=r") (minus:DI (const_int 63) - (clz:DI (match_operand:DI 1 "nonimmediate_operand" "rm")))) - (clobber (reg:CC FLAGS_REG))] + (clz:DI (match_dup 1))))] "TARGET_64BIT" "bsr{q}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") @@ -14545,10 +14547,12 @@ (set_attr "mode" "DI")]) (define_insn "bsr" - [(set (match_operand:SI 0 "register_operand" "=r") + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ (match_operand:SI 1 "nonimmediate_operand" "rm") + (const_int 0))) + (set (match_operand:SI 0 "register_operand" "=r") (minus:SI (const_int 31) - (clz:SI (match_operand:SI 1 "nonimmediate_operand" "rm")))) - (clobber (reg:CC FLAGS_REG))] + (clz:SI (match_dup 1))))] "" "bsr{l}\t{%1, %0|%0, %1}" [(set_attr "type" "alu1") @@ -14556,25 +14560,15 @@ (set_attr "znver1_decode" "vector") (set_attr "mode" "SI")]) -(define_insn "*bsrhi" - [(set (match_operand:HI 0 "register_operand" "=r") - (minus:HI (const_int 15) - (clz:HI (match_operand:HI 1 "nonimmediate_operand" "rm")))) - (clobber (reg:CC FLAGS_REG))] - "" - "bsr{w}\t{%1, %0|%0, %1}" - [(set_attr "type" "alu1") - (set_attr "prefix_0f" "1") - (set_attr "znver1_decode" "vector") - (set_attr "mode" "HI")]) - (define_expand "clz<mode>2" [(parallel - [(set (match_operand:SWI48 0 "register_operand") + [(set (reg:CCZ FLAGS_REG) + (compare:CCZ (match_operand:SWI48 1 "nonimmediate_operand" "rm") + (const_int 0))) + (set (match_operand:SWI48 0 "register_operand") (minus:SWI48 (match_dup 2) - (clz:SWI48 (match_operand:SWI48 1 "nonimmediate_operand")))) - (clobber (reg:CC FLAGS_REG))]) + (clz:SWI48 (match_dup 1))))]) (parallel [(set (match_dup 0) (xor:SWI48 (match_dup 0) (match_dup 2))) (clobber (reg:CC FLAGS_REG))])] diff --git a/gcc/testsuite/gcc.target/i386/pr101175.c b/gcc/testsuite/gcc.target/i386/pr101175.c new file mode 100644 index 00000000000..ed7a08110a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101175.c @@ -0,0 +1,28 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -mlzcnt" } */ +/* { dg-require-effective-target lzcnt } */ + +#include "lzcnt-check.h" + +static int +foo (unsigned int v) +{ + return v ? __builtin_clz (v) : 32; +} + +/* returns -1 if x == 0 */ +int +__attribute__ ((noinline, noclone)) +bar (unsigned int x) +{ + return 31 - foo (x); +} + +static void +lzcnt_test () +{ + int r = bar (0); + + if (r != -1) + abort (); +}
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