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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work056)] Deal with zero/sign extend to IEEE 128-bit on 32-bit.
Date: Tue, 29 Jun 2021 17:05:27 +0000 (GMT)	[thread overview]
Message-ID: <20210629170527.3415D3858C27@sourceware.org> (raw)

https://gcc.gnu.org/g:6d4d33682cc255dabccc57872e6ed3fc60bf2985

commit 6d4d33682cc255dabccc57872e6ed3fc60bf2985
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Tue Jun 29 13:05:06 2021 -0400

    Deal with zero/sign extend to IEEE 128-bit on 32-bit.
    
    gcc/
    2021-06-29  Michael Meissner  <meissner@linux.ibm.com>
    
            * config/rs6000/rs6000.md (float_<mode>si2_hw): Correctly sign
            extend SImode to DImode for 32-bit.
            (floatuns_<mode>si2_hw): Correctly zero extend SImode to DImode
            for 32-bit.

Diff:
---
 gcc/config/rs6000/rs6000.md | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 3ba0beaee32..55e8b22ee83 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -14726,9 +14726,7 @@
   "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
   "#"
   "&& 1"
-  [(set (match_dup 2)
-	(sign_extend:DI (match_dup 1)))
-   (set (match_dup 0)
+  [(set (match_dup 0)
 	(float:IEEE128 (match_dup 2)))]
 {
   if (GET_CODE (operands[2]) == SCRATCH)
@@ -14736,6 +14734,8 @@
 
   if (MEM_P (operands[1]))
     operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
+
+  convert_move (operands[2], operands[1], false);
 })
 
 (define_insn_and_split "float<QHI:mode><IEEE128:mode>2"
@@ -14792,9 +14792,7 @@
   "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (<MODE>mode)"
   "#"
   "&& 1"
-  [(set (match_dup 2)
-	(zero_extend:DI (match_dup 1)))
-   (set (match_dup 0)
+  [(set (match_dup 0)
 	(float:IEEE128 (match_dup 2)))]
 {
   if (GET_CODE (operands[2]) == SCRATCH)
@@ -14802,6 +14800,8 @@
 
   if (MEM_P (operands[1]))
     operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]);
+
+  convert_move (operands[2], operands[1], true);
 })
 
 (define_insn_and_split "floatuns<QHI:mode><IEEE128:mode>2"


                 reply	other threads:[~2021-06-29 17:05 UTC|newest]

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