From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 3415D3858C27; Tue, 29 Jun 2021 17:05:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3415D3858C27 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work056)] Deal with zero/sign extend to IEEE 128-bit on 32-bit. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work056 X-Git-Oldrev: 33c22ce3538d1724d46710a7d12757641b51da20 X-Git-Newrev: 6d4d33682cc255dabccc57872e6ed3fc60bf2985 Message-Id: <20210629170527.3415D3858C27@sourceware.org> Date: Tue, 29 Jun 2021 17:05:27 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 29 Jun 2021 17:05:27 -0000 https://gcc.gnu.org/g:6d4d33682cc255dabccc57872e6ed3fc60bf2985 commit 6d4d33682cc255dabccc57872e6ed3fc60bf2985 Author: Michael Meissner Date: Tue Jun 29 13:05:06 2021 -0400 Deal with zero/sign extend to IEEE 128-bit on 32-bit. gcc/ 2021-06-29 Michael Meissner * config/rs6000/rs6000.md (float_si2_hw): Correctly sign extend SImode to DImode for 32-bit. (floatuns_si2_hw): Correctly zero extend SImode to DImode for 32-bit. Diff: --- gcc/config/rs6000/rs6000.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3ba0beaee32..55e8b22ee83 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -14726,9 +14726,7 @@ "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "#" "&& 1" - [(set (match_dup 2) - (sign_extend:DI (match_dup 1))) - (set (match_dup 0) + [(set (match_dup 0) (float:IEEE128 (match_dup 2)))] { if (GET_CODE (operands[2]) == SCRATCH) @@ -14736,6 +14734,8 @@ if (MEM_P (operands[1])) operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]); + + convert_move (operands[2], operands[1], false); }) (define_insn_and_split "float2" @@ -14792,9 +14792,7 @@ "TARGET_FLOAT128_HW && FLOAT128_IEEE_P (mode)" "#" "&& 1" - [(set (match_dup 2) - (zero_extend:DI (match_dup 1))) - (set (match_dup 0) + [(set (match_dup 0) (float:IEEE128 (match_dup 2)))] { if (GET_CODE (operands[2]) == SCRATCH) @@ -14802,6 +14800,8 @@ if (MEM_P (operands[1])) operands[1] = rs6000_force_indexed_or_indirect_mem (operands[1]); + + convert_move (operands[2], operands[1], true); }) (define_insn_and_split "floatuns2"