public inbox for gcc-cvs@sourceware.org help / color / mirror / Atom feed
From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-2135] Generate 128-bit int divide/modulus on power10. Date: Thu, 8 Jul 2021 01:56:22 +0000 (GMT) [thread overview] Message-ID: <20210708015622.024313846077@sourceware.org> (raw) https://gcc.gnu.org/g:852b11da11a181df517c0348df044354ff0656d6 commit r12-2135-g852b11da11a181df517c0348df044354ff0656d6 Author: Michael Meissner <meissner@linux.ibm.com> Date: Wed Jul 7 21:55:38 2021 -0400 Generate 128-bit int divide/modulus on power10. This patch adds support for the VDIVSQ, VDIVUQ, VMODSQ, and VMODUQ instructions to do 128-bit arithmetic. 2021-07-07 Michael Meissner <meissner@linux.ibm.com> gcc/ PR target/100809 * config/rs6000/rs6000.md (udivti3): New insn. (divti3): New insn. (umodti3): New insn. (modti3): New insn. gcc/testsuite/ PR target/100809 * gcc.target/powerpc/p10-vdivq-vmodq.c: New test. Diff: --- gcc/config/rs6000/rs6000.md | 34 ++++++++++++++++++++++ gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c | 27 +++++++++++++++++ 2 files changed, 61 insertions(+) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e84d0311cc2..2368153269c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -3234,6 +3234,14 @@ [(set_attr "type" "div") (set_attr "size" "<bits>")]) +(define_insn "udivti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (udiv:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vdivuq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) ;; For powers of two we can do sra[wd]i/addze for divide and then adjust for ;; modulus. If it isn't a power of two, force operands into register and do @@ -3324,6 +3332,15 @@ (set_attr "length" "8,12") (set_attr "cell_micro" "not")]) +(define_insn "divti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (div:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vdivsq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) + (define_expand "mod<mode>3" [(set (match_operand:GPR 0 "gpc_reg_operand") (mod:GPR (match_operand:GPR 1 "gpc_reg_operand") @@ -3424,6 +3441,23 @@ (minus:GPR (match_dup 1) (match_dup 3)))]) +(define_insn "umodti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (umod:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vmoduq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) + +(define_insn "modti3" + [(set (match_operand:TI 0 "altivec_register_operand" "=v") + (mod:TI (match_operand:TI 1 "altivec_register_operand" "v") + (match_operand:TI 2 "altivec_register_operand" "v")))] + "TARGET_POWER10 && TARGET_POWERPC64" + "vmodsq %0,%1,%2" + [(set_attr "type" "vecdiv") + (set_attr "size" "128")]) \f ;; Logical instructions ;; The logical instructions are mostly combined by using match_operator, diff --git a/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c new file mode 100644 index 00000000000..84685e5ff43 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/p10-vdivq-vmodq.c @@ -0,0 +1,27 @@ +/* { dg-require-effective-target int128 } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +unsigned __int128 u_div(unsigned __int128 a, unsigned __int128 b) +{ + return a/b; +} + +unsigned __int128 u_mod(unsigned __int128 a, unsigned __int128 b) +{ + return a%b; +} +__int128 s_div(__int128 a, __int128 b) +{ + return a/b; +} + +__int128 s_mod(__int128 a, __int128 b) +{ + return a%b; +} + +/* { dg-final { scan-assembler {\mvdivsq\M} } } */ +/* { dg-final { scan-assembler {\mvdivuq\M} } } */ +/* { dg-final { scan-assembler {\mvmodsq\M} } } */ +/* { dg-final { scan-assembler {\mvmoduq\M} } } */
reply other threads:[~2021-07-08 1:56 UTC|newest] Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210708015622.024313846077@sourceware.org \ --to=meissner@gcc.gnu.org \ --cc=gcc-cvs@gcc.gnu.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).