From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2063) id 530D53AAB030; Fri, 9 Jul 2021 03:02:23 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 530D53AAB030 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Kewen Lin To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-2182] rs6000: Support [u]mod3 for vector modulo insns X-Act-Checkin: gcc X-Git-Author: Kewen Lin X-Git-Refname: refs/heads/master X-Git-Oldrev: df85baa5687170cbca8450a59cf17f3157b1d61d X-Git-Newrev: 062c762ef264dca89d01ebca2ef023ea91f31d50 Message-Id: <20210709030223.530D53AAB030@sourceware.org> Date: Fri, 9 Jul 2021 03:02:23 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 09 Jul 2021 03:02:23 -0000 https://gcc.gnu.org/g:062c762ef264dca89d01ebca2ef023ea91f31d50 commit r12-2182-g062c762ef264dca89d01ebca2ef023ea91f31d50 Author: Kewen Lin Date: Thu Jul 8 22:00:24 2021 -0500 rs6000: Support [u]mod3 for vector modulo insns This patch is to make Power10 newly introduced vector modulo instructions exploited in vectorized loops, it just simply renames existing define_insns as standard pattern names. gcc/ChangeLog: * config/rs6000/vsx.md (mods_): Rename to... (mod3): ... this. (modu_): Rename to... (umod3): ... this. * config/rs6000/rs6000-builtin.def (MODS_V2DI, MODS_V4SI, MODU_V2DI, MODU_V4SI): Adjust. gcc/testsuite/ChangeLog: * gcc.target/powerpc/mod-vectorize.c: New test. Diff: --- gcc/config/rs6000/rs6000-builtin.def | 8 ++--- gcc/config/rs6000/vsx.md | 4 +-- gcc/testsuite/gcc.target/powerpc/mod-vectorize.c | 46 ++++++++++++++++++++++++ 3 files changed, 52 insertions(+), 6 deletions(-) diff --git a/gcc/config/rs6000/rs6000-builtin.def b/gcc/config/rs6000/rs6000-builtin.def index 6270444ef70..a0dfefccd43 100644 --- a/gcc/config/rs6000/rs6000-builtin.def +++ b/gcc/config/rs6000/rs6000-builtin.def @@ -3031,10 +3031,10 @@ BU_P10V_AV_2 (DIVS_V4SI, "vdivsw", CONST, divv4si3) BU_P10V_AV_2 (DIVS_V2DI, "vdivsd", CONST, divv2di3) BU_P10V_AV_2 (DIVU_V4SI, "vdivuw", CONST, udivv4si3) BU_P10V_AV_2 (DIVU_V2DI, "vdivud", CONST, udivv2di3) -BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, mods_v2di) -BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, mods_v4si) -BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, modu_v2di) -BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, modu_v4si) +BU_P10V_AV_2 (MODS_V2DI, "vmodsd", CONST, modv2di3) +BU_P10V_AV_2 (MODS_V4SI, "vmodsw", CONST, modv4si3) +BU_P10V_AV_2 (MODU_V2DI, "vmodud", CONST, umodv2di3) +BU_P10V_AV_2 (MODU_V4SI, "vmoduw", CONST, umodv4si3) BU_P10V_AV_2 (MULHS_V2DI, "vmulhsd", CONST, mulhs_v2di) BU_P10V_AV_2 (MULHS_V4SI, "vmulhsw", CONST, mulhs_v4si) BU_P10V_AV_2 (MULHU_V2DI, "vmulhud", CONST, mulhu_v2di) diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index f2260badf70..f622873d758 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -6333,7 +6333,7 @@ [(set_attr "type" "vecdiv") (set_attr "size" "")]) -(define_insn "mods_" +(define_insn "mod3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (mod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] @@ -6342,7 +6342,7 @@ [(set_attr "type" "vecdiv") (set_attr "size" "")]) -(define_insn "modu_" +(define_insn "umod3" [(set (match_operand:VIlong 0 "vsx_register_operand" "=v") (umod:VIlong (match_operand:VIlong 1 "vsx_register_operand" "v") (match_operand:VIlong 2 "vsx_register_operand" "v")))] diff --git a/gcc/testsuite/gcc.target/powerpc/mod-vectorize.c b/gcc/testsuite/gcc.target/powerpc/mod-vectorize.c new file mode 100644 index 00000000000..4d4f5cd6446 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/mod-vectorize.c @@ -0,0 +1,46 @@ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2 -ftree-vectorize -fno-vect-cost-model -fno-unroll-loops -fdump-tree-vect-details" } */ + +/* Test vectorizer can exploit ISA 3.1 instructions Vector Modulo + Signed/Unsigned Word/Doubleword for word/doubleword modulo operations. */ + +#define N 128 + +extern signed int si_a[N], si_b[N], si_c[N]; +extern unsigned int ui_a[N], ui_b[N], ui_c[N]; +extern signed long long sd_a[N], sd_b[N], sd_c[N]; +extern unsigned long long ud_a[N], ud_b[N], ud_c[N]; + +__attribute__ ((noipa)) void +test_si () +{ + for (int i = 0; i < N; i++) + si_c[i] = si_a[i] % si_b[i]; +} + +__attribute__ ((noipa)) void +test_ui () +{ + for (int i = 0; i < N; i++) + ui_c[i] = ui_a[i] % ui_b[i]; +} + +__attribute__ ((noipa)) void +test_sd () +{ + for (int i = 0; i < N; i++) + sd_c[i] = sd_a[i] % sd_b[i]; +} + +__attribute__ ((noipa)) void +test_ud () +{ + for (int i = 0; i < N; i++) + ud_c[i] = ud_a[i] % ud_b[i]; +} + +/* { dg-final { scan-tree-dump-times "vectorized 1 loops" 4 "vect" } } */ +/* { dg-final { scan-assembler-times {\mvmodsw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvmoduw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvmodsd\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mvmodud\M} 1 } } */