public inbox for gcc-cvs@sourceware.org help / color / mirror / Atom feed
From: H.J. Lu <hjl@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-2296] x86: Don't enable UINTR in 32-bit mode Date: Wed, 14 Jul 2021 12:24:40 +0000 (GMT) [thread overview] Message-ID: <20210714122440.092B13854830@sourceware.org> (raw) https://gcc.gnu.org/g:cc11b924bfe7752edbba052ca71653f46a60887a commit r12-2296-gcc11b924bfe7752edbba052ca71653f46a60887a Author: H.J. Lu <hjl.tools@gmail.com> Date: Fri Jul 9 09:16:01 2021 -0700 x86: Don't enable UINTR in 32-bit mode UINTR is available only in 64-bit mode. Since the codegen target is unknown when the the gcc driver is processing -march=native, to properly handle UINTR for -march=native: 1. Pass "arch [32|64]" and "tune [32|64]" to host_detect_local_cpu to indicate 32-bit and 64-bit codegen. 2. Change ix86_option_override_internal to enable UINTR only in 64-bit mode for -march=CPU when PTA_CPU includes PTA_UINTR. gcc/ PR target/101395 * config/i386/driver-i386.c (host_detect_local_cpu): Check "arch [32|64]" and "tune [32|64]" for 32-bit and 64-bit codegen. Enable UINTR only for 64-bit codegen. * config/i386/i386-options.c (ix86_option_override_internal::DEF_PTA): Skip PTA_UINTR if not in 64-bit mode. * config/i386/i386.h (ARCH_ARG): New. (CC1_CPU_SPEC): Pass "[arch|tune] 32" for 32-bit codegen and "[arch|tune] 64" for 64-bit codegen. gcc/testsuite/ PR target/101395 * gcc.target/i386/pr101395-1.c: New test. * gcc.target/i386/pr101395-2.c: Likewise. * gcc.target/i386/pr101395-3.c: Likewise. Diff: --- gcc/config/i386/driver-i386.c | 25 +++++++++++++++++++------ gcc/config/i386/i386-options.c | 1 + gcc/config/i386/i386.h | 7 ++++--- gcc/testsuite/gcc.target/i386/pr101395-1.c | 12 ++++++++++++ gcc/testsuite/gcc.target/i386/pr101395-2.c | 22 ++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr101395-3.c | 6 ++++++ 6 files changed, 64 insertions(+), 9 deletions(-) diff --git a/gcc/config/i386/driver-i386.c b/gcc/config/i386/driver-i386.c index dd9236616b4..f844a168ddb 100644 --- a/gcc/config/i386/driver-i386.c +++ b/gcc/config/i386/driver-i386.c @@ -370,9 +370,9 @@ detect_caches_intel (bool xeon_mp, unsigned max_level, } /* This will be called by the spec parser in gcc.c when it sees - a %:local_cpu_detect(args) construct. Currently it will be called - with either "arch" or "tune" as argument depending on if -march=native - or -mtune=native is to be substituted. + a %:local_cpu_detect(args) construct. Currently it will be + called with either "arch [32|64]" or "tune [32|64]" as argument + depending on if -march=native or -mtune=native is to be substituted. It returns a string containing new command line parameters to be put at the place of the above two options, depending on what CPU @@ -401,7 +401,7 @@ const char *host_detect_local_cpu (int argc, const char **argv) unsigned int l2sizekb = 0; - if (argc < 1) + if (argc < 2) return NULL; arch = !strcmp (argv[0], "arch"); @@ -409,6 +409,15 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (!arch && strcmp (argv[0], "tune")) return NULL; + bool codegen_x86_64; + + if (!strcmp (argv[1], "32")) + codegen_x86_64 = false; + else if (!strcmp (argv[1], "64")) + codegen_x86_64 = true; + else + return NULL; + struct __processor_model cpu_model = { }; struct __processor_model2 cpu_model2 = { }; unsigned int cpu_features2[SIZE_OF_CPU_FEATURES] = { }; @@ -804,8 +813,12 @@ const char *host_detect_local_cpu (int argc, const char **argv) if (isa_names_table[i].option) { if (has_feature (isa_names_table[i].feature)) - options = concat (options, " ", - isa_names_table[i].option, NULL); + { + if (codegen_x86_64 + || isa_names_table[i].feature != FEATURE_UINTR) + options = concat (options, " ", + isa_names_table[i].option, NULL); + } else options = concat (options, neg_option, isa_names_table[i].option + 2, NULL); diff --git a/gcc/config/i386/i386-options.c b/gcc/config/i386/i386-options.c index 7a35c468da3..7cba655595e 100644 --- a/gcc/config/i386/i386-options.c +++ b/gcc/config/i386/i386-options.c @@ -2109,6 +2109,7 @@ ix86_option_override_internal (bool main_args_p, #define DEF_PTA(NAME) \ if (((processor_alias_table[i].flags & PTA_ ## NAME) != 0) \ && PTA_ ## NAME != PTA_64BIT \ + && (TARGET_64BIT || PTA_ ## NAME != PTA_UINTR) \ && !TARGET_EXPLICIT_ ## NAME ## _P (opts)) \ SET_TARGET_ ## NAME (opts); #include "i386-isa.def" diff --git a/gcc/config/i386/i386.h b/gcc/config/i386/i386.h index 8c3eace56da..324e8a952d9 100644 --- a/gcc/config/i386/i386.h +++ b/gcc/config/i386/i386.h @@ -576,10 +576,11 @@ extern const char *host_detect_local_cpu (int argc, const char **argv); #ifndef HAVE_LOCAL_CPU_DETECT #define CC1_CPU_SPEC CC1_CPU_SPEC_1 #else +#define ARCH_ARG "%{" OPT_ARCH64 ":64;:32}" #define CC1_CPU_SPEC CC1_CPU_SPEC_1 \ -"%{march=native:%>march=native %:local_cpu_detect(arch) \ - %{!mtune=*:%>mtune=native %:local_cpu_detect(tune)}} \ -%{mtune=native:%>mtune=native %:local_cpu_detect(tune)}" +"%{march=native:%>march=native %:local_cpu_detect(arch " ARCH_ARG ") \ + %{!mtune=*:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}} \ +%{mtune=native:%>mtune=native %:local_cpu_detect(tune " ARCH_ARG ")}" #endif #endif \f diff --git a/gcc/testsuite/gcc.target/i386/pr101395-1.c b/gcc/testsuite/gcc.target/i386/pr101395-1.c new file mode 100644 index 00000000000..74c8bfe891a --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101395-1.c @@ -0,0 +1,12 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=sapphirerapids" } */ + +#ifdef __x86_64__ +# ifndef __UINTR__ +# error UINTR is not enabled for Sapphirerapids +# endif +#else +# ifdef __UINTR__ +# error UINTR is not usable in 32-bit mode +# endif +#endif diff --git a/gcc/testsuite/gcc.target/i386/pr101395-2.c b/gcc/testsuite/gcc.target/i386/pr101395-2.c new file mode 100644 index 00000000000..f2b677f8c80 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101395-2.c @@ -0,0 +1,22 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=native" } */ + +int +main () +{ + if (__builtin_cpu_supports ("uintr")) + { +#ifdef __x86_64__ +# ifndef __UINTR__ + __builtin_abort (); +# endif +#else +# ifdef __UINTR__ + __builtin_abort (); +# endif +#endif + return 0; + } + + return 0; +} diff --git a/gcc/testsuite/gcc.target/i386/pr101395-3.c b/gcc/testsuite/gcc.target/i386/pr101395-3.c new file mode 100644 index 00000000000..bc6ab423c93 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr101395-3.c @@ -0,0 +1,6 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -march=native -mno-uintr" } */ + +#ifdef __UINTR__ +# error UINTR should be disabled +#endif
reply other threads:[~2021-07-14 12:24 UTC|newest] Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=20210714122440.092B13854830@sourceware.org \ --to=hjl@gcc.gnu.org \ --cc=gcc-cvs@gcc.gnu.org \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).