From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id D8A2139890AF; Tue, 20 Jul 2021 16:57:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org D8A2139890AF MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-2417] PR 100167: Fix vector long long multiply/divide tests on power10. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/heads/master X-Git-Oldrev: e0e82856d535f56c916382f892ed2435dde54d4d X-Git-Newrev: 7fcb33455c9dc9359d98cd6bffe7f32f282ed713 Message-Id: <20210720165728.D8A2139890AF@sourceware.org> Date: Tue, 20 Jul 2021 16:57:28 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 20 Jul 2021 16:57:29 -0000 https://gcc.gnu.org/g:7fcb33455c9dc9359d98cd6bffe7f32f282ed713 commit r12-2417-g7fcb33455c9dc9359d98cd6bffe7f32f282ed713 Author: Michael Meissner Date: Tue Jul 20 12:56:19 2021 -0400 PR 100167: Fix vector long long multiply/divide tests on power10. This patch updates the vector long long multiply and divide tests to supply the correct code information if power10 code generation is used. 2021-06-18 Michael Meissner gcc/testsuite/ PR testsuite/100167 * gcc.target/powerpc/fold-vec-div-longlong.c: Fix expected code generation on power10. * gcc.target/powerpc/fold-vec-mult-longlong.c: Likewise. Diff: --- gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c | 7 +++++-- gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c | 7 +++++-- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c index 312e984d3cc..f6a9b290ae5 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-div-longlong.c @@ -19,5 +19,8 @@ test6 (vector unsigned long long x, vector unsigned long long y) { return vec_div (x, y); } -/* { dg-final { scan-assembler-times {\mdivd\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mdivdu\M} 2 } } */ + +/* { dg-final { scan-assembler-times {\mdivd\M} 2 { target { ! has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mdivdu\M} 2 { target { ! has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mvdivsd\M} 1 { target { has_arch_pwr10 } } } } */ +/* { dg-final { scan-assembler-times {\mvdivud\M} 1 { target { has_arch_pwr10 } } } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c index 38dba9f5023..dff073d372d 100644 --- a/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/fold-vec-mult-longlong.c @@ -20,5 +20,8 @@ test6 (vector unsigned long long x, vector unsigned long long y) return vec_mul (x, y); } -/* { dg-final { scan-assembler-times "\[ \t\]mulld " 4 { target lp64 } } } */ - +/* Power10 can generate the vmulld instruction even in 32-bit. Before power10, + we limit the code to lp64, since 32-bit cannot generate the mulld + instruction. */ +/* { dg-final { scan-assembler-times {\mmulld\M} 4 { target { lp64 && { ! has_arch_pwr10 } } } } } */ +/* { dg-final { scan-assembler-times {\mvmulld\M} 2 { target { has_arch_pwr10 } } } } */