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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work061)] Revert patches. Date: Thu, 22 Jul 2021 03:09:49 +0000 (GMT) [thread overview] Message-ID: <20210722030949.5407B3969831@sourceware.org> (raw) https://gcc.gnu.org/g:0b08e96c30a426414d87f3391a5f796fd9702f2f commit 0b08e96c30a426414d87f3391a5f796fd9702f2f Author: Michael Meissner <meissner@linux.ibm.com> Date: Wed Jul 21 23:08:48 2021 -0400 Revert patches. 2021-07-21 Michael Meissner <meissner@linux.ibm.com> gcc/ Revert patches. * config/rs6000/constraints.md (eF): New constraint. * config/rs6000/predicates.md (easy_fp_constant): If we can load the scalar constant with XXSPLTIDP, the floating point constant is easy. (xxspltidp_operand): New predicate. (easy_vector_constant): If we can generate XXSPLTIDP, mark the vector constant as easy. * config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add -mxxspltidp support. (POWERPC_MASKS): Add -mxxspltidp support. * config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New declaration. * config/rs6000/rs6000.c (const_vector_element_all_same): New function. (xxspltidp_constant_p): New function. (output_vec_const_move): Add support for XXSPLTIDP. (rs6000_opt_masks): Add -mxxspltidp support. (rs6000_emit_xxspltidp_v2df): Change function to implement the XXSPLTIDP instruction. * config/rs6000/rs6000.h (TARGET_XXSPLTIDP): New macro. * config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP support. (mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support. (mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support. * config/rs6000/rs6000.opt (-mxxspltidp): New switch. * config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID to UNSPEC_XXSPLTIDP to match the instruction. (xxspltidp_v2df): Use 'use' for the expand arguments, instead of writing out an insn. (xxspltidp_v2df_inst): Delete. (XXSPLTIDP): New mode iterator. (xxspltidp_<mode>_internal1): New define_insn_and_split. (xxspltidp_<mode>_internal2): New define_insn. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-sf.c: New test. * gcc.target/powerpc/vec-splat-constant-df.c: New test. * gcc.target/powerpc/vec-splat-constant-v2df.c: New test. gcc/ Revert patches. * config/rs6000/predicates.md (xxspltiw_operand): New predicate. (easy_vector_constant): If we can use XXSPLTIW, the vector constant is easy. * config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate XXSPLTIW, don't generate a XXSPLTIB and an extend instruction. (output_vec_const_move): Add support for loading up vector constants with XXSPLTIW. * config/rs6000/rs6000.h (TARGET_XXSPLTIW): New macro. (SIGN_EXTEND_8BIT): New macro. (SIGN_EXTEND_16BIT): New macro. (SIGN_EXTEND_32BIT): New macro. * config/rs6000/rs6000.opt (-mxxspltiw): New debug switch. * config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete. (xxspltiw_v8hi): New insn. (xxspltiw_v4si): Rewrite to generate a vector constant. (xxspltiw_v4sf): Rewrite to generate a vector constant. (xxspltiw_v4si_inst): Delete. (xxspltiw_v4sf_inst): Delete. (xxspltiw_v8hi_dup): New insn. (xxspltiw_v4si_dup): New insn. (xxspltiw_v4sf_dup): New insn. (XXSPLTIW): New mode iterator. (XXSPLTIW splitter): New insn splitter for XXSPLTIW. gcc/testsuite/ Revert patches. * gcc.target/powerpc/pr86731-fwrapv.c: Update insn counts on power10. * gcc.target/powerpc/vec-splati-runnable.c: Update insn counts. * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. Diff: --- gcc/config/rs6000/constraints.md | 5 - gcc/config/rs6000/predicates.md | 50 ------ gcc/config/rs6000/rs6000-protos.h | 1 - gcc/config/rs6000/rs6000.c | 104 +---------- gcc/config/rs6000/rs6000.h | 26 --- gcc/config/rs6000/rs6000.md | 52 ++---- gcc/config/rs6000/rs6000.opt | 8 - gcc/config/rs6000/vsx.md | 198 +++++---------------- gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c | 9 +- .../gcc.target/powerpc/vec-splat-constant-df.c | 60 ------- .../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ------- .../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ------- .../gcc.target/powerpc/vec-splat-constant-v4sf.c | 66 ------- .../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ------ .../gcc.target/powerpc/vec-splat-constant-v8hi.c | 53 ------ .../gcc.target/powerpc/vec-splati-runnable.c | 4 +- 16 files changed, 71 insertions(+), 740 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index e1fadd63580..561ce9797af 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -208,11 +208,6 @@ (and (match_code "const_int") (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) -;; SF/DF/V2DF scalar or vector constant that can be loaded with XXSPLTIDP -(define_constraint "eF" - "A vector constant that can be loaded with the XXSPLTIDP instruction." - (match_operand 0 "xxspltidp_operand")) - ;; 34-bit signed integer constant (define_constraint "eI" "A signed 34-bit integer constant if prefixed instructions are supported." diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 5d84723e6a1..956e42bc514 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -601,11 +601,6 @@ if (TARGET_VSX && op == CONST0_RTX (mode)) return 1; - /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can - be loaded with that instruction. */ - if (xxspltidp_operand (op, mode)) - return 1; - /* Otherwise consider floating point constants hard, so that the constant gets pushed to memory during the early RTL phases. This has the advantage that double precision constants that can be @@ -645,45 +640,6 @@ return num_insns == 1; }) -;; Return 1 if the operand is a CONST_VECTOR that can be loaded with the -;; XXSPLTIW instruction. Do not return 1 if the constant can be generated with -;; XXSPLTIB or VSPLTIS{H,W} -(define_predicate "xxspltiw_operand" - (match_code "const_vector") -{ - if (!TARGET_XXSPLTIW) - return false; - - if (mode != V8HImode && mode != V4SImode && mode != V4SFmode) - return false; - - rtx element = CONST_VECTOR_ELT (op, 0); - for (size_t i = 1; i < GET_MODE_NUNITS (mode); i++) - if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, i))) - return false; - - if (element == CONST0_RTX (GET_MODE_INNER (mode))) - return false; - - if (CONST_INT_P (element) && EASY_VECTOR_15 (INTVAL (element))) - return false; - - return true; -}) - -;; Return 1 if operand is a SF/DF CONST_DOUBLE or V2DF CONST_VECTOR that can be -;; loaded via the ISA 3.1 XXSPLTIDP instruction. Do not return true if the -;; value is 0.0, since that is easy to generate without using XXSPLTIDP. -(define_predicate "xxspltidp_operand" - (match_code "const_double,const_vector,vec_duplicate") -{ - if (op == CONST0_RTX (mode)) - return false; - - HOST_WIDE_INT value = 0; - return xxspltidp_constant_p (op, mode, &value); -}) - ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a ;; vector register without using memory. (define_predicate "easy_vector_constant" @@ -697,12 +653,6 @@ if (zero_constant (op, mode) || all_ones_constant (op, mode)) return true; - if (xxspltiw_operand (op, mode)) - return true; - - if (xxspltidp_operand (op, mode)) - return true; - if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index ce8e993100e..14f6b313105 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -32,7 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, extern int easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); -extern bool xxspltidp_constant_p (rtx, machine_mode, HOST_WIDE_INT *); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 3b41fc6230a..6b7baf36c2b 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6506,11 +6506,9 @@ xxspltib_constant_p (rtx op, /* See if we could generate vspltisw/vspltish directly instead of xxspltib + sign extend. Special case 0/-1 to allow getting any VSX register instead - of an Altivec register. Also if we can generate a XXSPLTIW instruction, - don't emit a XXSPLTIB and an extend instruction. */ - if ((mode == V4SImode || mode == V8HImode) - && !IN_RANGE (value, -1, 0) - && (EASY_VECTOR_15 (value) || TARGET_XXSPLTIW)) + of an Altivec register. */ + if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0) + && EASY_VECTOR_15 (value)) return false; /* Return # of instructions and the constant byte for XXSPLTIB. */ @@ -6527,96 +6525,6 @@ xxspltib_constant_p (rtx op, return true; } -/* Return the element of a constant vector whose elements are all the same. In - addition if VEC_DUPLICATE is used, return the element being duplicated. If - neither is true, return NULL_RTX. */ - -static rtx -const_vector_element_all_same (rtx op) -{ - if (GET_CODE (op) == VEC_DUPLICATE) - { - rtx element = XEXP (op, 0); - return (CONST_INT_P (element) || CONST_DOUBLE_P (element) - ? element - : NULL_RTX); - } - - else if (GET_CODE (op) == CONST_VECTOR) - { - machine_mode mode = GET_MODE (op); - size_t n_elts = GET_MODE_NUNITS (mode); - rtx element = CONST_VECTOR_ELT (op, 0); - - for (size_t i = 1; i < n_elts; i++) - if (!rtx_equal_p (element, CONST_VECTOR_ELT (op, 1))) - return NULL_RTX; - - return element; - } - - return NULL_RTX; -} - -/* Return true if OP is of the given MODE and can be synthesized with ISA 3.1 - XXSPLTIDP instruction. - - Return the constant that is being split via CONSTANT_PTR to use in the - XXSPLTIDP instruction. */ - -bool -xxspltidp_constant_p (rtx op, - machine_mode mode, - HOST_WIDE_INT *constant_ptr) -{ - *constant_ptr = 0; - - if (!TARGET_XXSPLTIDP) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - rtx element = op; - if (mode == V2DFmode) - { - element = const_vector_element_all_same (op); - if (!element) - return false; - - mode = DFmode; - } - - if (mode != SFmode && mode != DFmode) - return false; - - if (GET_MODE (element) != mode) - return false; - - if (!CONST_DOUBLE_P (element)) - return false; - - /* Don't return true for 0.0 since that is easy to create without - XXSPLTIDP. */ - if (element == CONST0_RTX (mode)) - return false; - - /* If the value doesn't fit in a SFmode, exactly, we can't use XXSPLTIDP. */ - const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (element); - if (!exact_real_truncate (SFmode, rv)) - return 0; - - long value; - REAL_VALUE_TO_TARGET_SINGLE (*rv, value); - - /* Test for SFmode denormal (exponent is 0, mantissa field is non-zero). */ - if (((value & 0x7F800000) == 0) && ((value & 0x7FFFFF) != 0)) - return false; - - *constant_ptr = value; - return true; -} - const char * output_vec_const_move (rtx *operands) { @@ -6661,10 +6569,6 @@ output_vec_const_move (rtx *operands) gcc_unreachable (); } - if (xxspltiw_operand (vec, mode) - || xxspltidp_operand (vec, mode)) - return "#"; - if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -28120,7 +28024,7 @@ rs6000_emit_xxspltidp_v2df (rtx dst, long value) inform (input_location, "the result for the xxspltidp instruction " "is undefined for subnormal input values"); - emit_insn (gen_xxspltidp_v2df_internal2 (dst, GEN_INT (value))); + emit_insn( gen_xxspltidp_v2df_inst (dst, GEN_INT (value))); } /* Implement TARGET_ASM_GENERATE_PIC_ADDR_DIFF_VEC. */ diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h index 9cd0e654c81..c5f38f26649 100644 --- a/gcc/config/rs6000/rs6000.h +++ b/gcc/config/rs6000/rs6000.h @@ -510,13 +510,6 @@ extern int rs6000_vector_align[]; #define TARGET_IBM128 (TARGET_FLOAT128_TYPE \ || (!TARGET_IEEEQUAD && TARGET_LONG_DOUBLE_128)) -/* Whether we can generate the XXSPLTI* prefixed instructions. We also need - VSX instructions to be generated. */ -#define TARGET_XXSPLTIDP (TARGET_XXSPLTIDP_DEBUG && TARGET_PREFIXED \ - && TARGET_VSX) -#define TARGET_XXSPLTIW (TARGET_XXSPLTIW_DEBUG && TARGET_PREFIXED \ - && TARGET_VSX) - /* In switching from using target_flags to using rs6000_isa_flags, the options machinery creates OPTION_MASK_<xxx> instead of MASK_<xxx>. For now map OPTION_MASK_<xxx> back into MASK_<xxx>. */ @@ -2620,22 +2613,3 @@ while (0) rs6000_asm_output_opcode (STREAM); \ } \ while (0) - -/* Provide macros for sign-extending values. */ -#if HOST_BITS_PER_CHAR == 8 -#define SIGN_EXTEND_8BIT(X) ((HOST_WIDE_INT)(signed char)(X)) -#else -#define SIGN_EXTEND_8BIT(X) ((((X) & 0xff) ^ 0x80) - 0x80) -#endif - -#if HOST_BITS_PER_SHORT == 16 -#define SIGN_EXTEND_16BIT(X) ((HOST_WIDE_INT)(short)(X)) -#else -#define SIGN_EXTEND_16BIT(X) ((((X) & 0xffff) ^ 0x8000) - 0x8000) -#endif - -#if HOST_BITS_PER_INT == 32 -#define SIGN_EXTEND_32BIT(X) ((HOST_WIDE_INT)(int)(X)) -#else -#define SIGN_EXTEND_32BIT(X) ((((X) & 0xffffffff) ^ 0x80000000) - 0x80000000) -#endif diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 0d2a9b56f6c..2368153269c 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7723,17 +7723,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT<x> MF<x> NOP XXSPLTIDP +;; MR MT<x> MF<x> NOP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h, wa") + !r, *c*l, !r, *h") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0, eF"))] + r, r, *h, 0"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7755,20 +7755,15 @@ mr %0,%1 mt%0 %1 mf%1 %0 - nop - #" + nop" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *, vecperm") + *, mtjmpr, mfjmpr, *") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *, p10") - (set_attr "prefixed" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *, *, yes")]) + *, *, *, *")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -8028,18 +8023,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR XXSPLTIDP +;; LWZ STW MR (define_insn "*mov<mode>_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, <f64_p9>, wY, <f64_av>, Z, <f64_vsx>, <f64_vsx>, !r, - Y, r, !r, wa") + Y, r, !r") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, <f64_p9>, Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>, - r, Y, r, eF"))] + r, Y, r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -8056,25 +8051,20 @@ # # # - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two, vecperm") + store, load, two") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8, *") + 8, 8, 8") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *, p10") - (set_attr "prefixed" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, yes")]) + *, *, *")]) ;; STW LWZ MR G-const H-const F-const @@ -8101,19 +8091,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFVSRD MTVSRD XXSPLTIDP +;; NOP MFVSRD MTVSRD (define_insn "*mov<mode>_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, <f64_p9>, wY, <f64_av>, Z, <f64_vsx>, <f64_vsx>, !r, YZ, r, !r, *c*l, !r, - *h, r, <f64_dm>, wa") + *h, r, <f64_dm>") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, <f64_p9>, Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>, r, YZ, r, r, *h, - 0, <f64_dm>, r, eF"))] + 0, <f64_dm>, r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -8135,24 +8125,18 @@ mf%1 %0 nop mfvsrd %0,%x1 - mtvsrd %x0,%1 - #" + mtvsrd %x0,%1" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr, vecperm") + *, mfvsr, mtvsr") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, *, *, *, *, *, - *, p8v, p8v, p10") - (set_attr "prefixed" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, *, yes")]) + *, p8v, p8v")]) ;; STD LD MR MT<SPR> MF<SPR> G-const ;; H-const F-const Special diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index b6455f6b1dc..0538db387dc 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -639,11 +639,3 @@ Enable instructions that guard against return-oriented programming attacks. mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. - -mxxspltidp -Target Undocumented Var(TARGET_XXSPLTIDP_DEBUG) Init(-1) Save -Generate (do not generate) XXSPLTIDP instructions. - -mxxspltiw -Target Undocumented Var(TARGET_XXSPLTIW_DEBUG) Init(1) Save -Generate (do not generate) XXSPLTIW instructions. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 3adf7e194d2..cacdd0d4cc8 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -373,7 +373,8 @@ UNSPEC_VDIVES UNSPEC_VDIVEU UNSPEC_XXEVAL - UNSPEC_XXSPLTIDP + UNSPEC_XXSPLTIW + UNSPEC_XXSPLTID UNSPEC_XXSPLTI32DX UNSPEC_XXBLEND UNSPEC_XXPERMX @@ -6406,10 +6407,41 @@ [(set_attr "type" "veccomplex")]) \f +;; XXSPLTIW built-in function support +(define_insn "xxspltiw_v4si" + [(set (match_operand:V4SI 0 "register_operand" "=wa") + (unspec:V4SI [(match_operand:SI 1 "s32bit_cint_operand" "n")] + UNSPEC_XXSPLTIW))] + "TARGET_POWER10" + "xxspltiw %x0,%1" + [(set_attr "type" "vecsimple") + (set_attr "prefixed" "yes")]) + +(define_expand "xxspltiw_v4sf" + [(set (match_operand:V4SF 0 "register_operand" "=wa") + (unspec:V4SF [(match_operand:SF 1 "const_double_operand" "n")] + UNSPEC_XXSPLTIW))] + "TARGET_POWER10" +{ + long value = rs6000_const_f32_to_i32 (operands[1]); + emit_insn (gen_xxspltiw_v4sf_inst (operands[0], GEN_INT (value))); + DONE; +}) + +(define_insn "xxspltiw_v4sf_inst" + [(set (match_operand:V4SF 0 "register_operand" "=wa") + (unspec:V4SF [(match_operand:SI 1 "c32bit_cint_operand" "n")] + UNSPEC_XXSPLTIW))] + "TARGET_POWER10" + "xxspltiw %x0,%1" + [(set_attr "type" "vecsimple") + (set_attr "prefixed" "yes")]) + ;; XXSPLTIDP built-in function support (define_expand "xxspltidp_v2df" - [(use (match_operand:V2DF 0 "register_operand" )) - (use (match_operand:SF 1 "const_double_operand"))] + [(set (match_operand:V2DF 0 "register_operand" ) + (unspec:V2DF [(match_operand:SF 1 "const_double_operand")] + UNSPEC_XXSPLTID))] "TARGET_POWER10" { long value = rs6000_const_f32_to_i32 (operands[1]); @@ -6417,6 +6449,15 @@ DONE; }) +(define_insn "xxspltidp_v2df_inst" + [(set (match_operand:V2DF 0 "register_operand" "=wa") + (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")] + UNSPEC_XXSPLTID))] + "TARGET_POWER10" + "xxspltidp %x0,%1" + [(set_attr "type" "vecsimple") + (set_attr "prefixed" "yes")]) + ;; XXSPLTI32DX built-in function support (define_expand "xxsplti32dx_v4si" [(set (match_operand:V4SI 0 "register_operand" "=wa") @@ -6548,154 +6589,3 @@ [(set_attr "type" "vecsimple") (set_attr "prefixed" "yes")]) -;; XXSPLTIW built-in function support. Convert to a vector constant, which -;; will then be optimized to the XXSPLTIW instruction. -(define_expand "xxspltiw_v4si" - [(use (match_operand:V4SI 0 "register_operand")) - (use (match_operand:SI 1 "s32bit_cint_operand"))] - "TARGET_POWER10" -{ - rtx op1 = operands[1]; - rtvec rv = gen_rtvec (4, op1, op1, op1, op1); - rtx vec_constant = gen_rtx_CONST_VECTOR (V4SImode, rv); - emit_move_insn (operands[0], vec_constant); -}) - -(define_expand "xxspltiw_v4sf" - [(use (match_operand:V4SF 0 "register_operand")) - (use (match_operand:SF 1 "const_double_operand"))] - "TARGET_POWER10" -{ - rtx op1 = operands[1]; - rtvec rv = gen_rtvec (4, op1, op1, op1, op1); - rtx vec_constant = gen_rtx_CONST_VECTOR (V4SFmode, rv); - emit_move_insn (operands[0], vec_constant); -}) - -;; XXSPLTIW support. Add support for the XXSPLTIW built-in functions, and to -;; use XXSPLTIW to load up vector V8HImode, V4SImode, and V4SFmode vector -;; constants where all elements are the the same. We special case loading up -;; integer -16..15 and floating point 0.0f, since we can use the shorter -;; XXSPLTIB, VSPLTISH, and VSPLTISW instructions. - -(define_insn "*xxspltiw_v8hi_dup" - [(set (match_operand:V8HI 0 "vsx_register_operand" "=wa,wa,v,wa") - (vec_duplicate:V8HI - (match_operand 1 "const_int_operand" "O,wM,wB,n")))] - "TARGET_XXSPLTIW" -{ - HOST_WIDE_INT sign_value = SIGN_EXTEND_16BIT (INTVAL (operands[1])); - - if (sign_value == 0) - return "xxspltib %x0,0"; - - if (sign_value == -1) - return "xxspltib %x0,255"; - - int r = reg_or_subregno (operands[0]); - if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value)) - { - operands[2] = GEN_INT (sign_value); - return "vspltish %0,%1"; - } - - HOST_WIDE_INT uns_value = sign_value & 0xffff; - operands[2] = GEN_INT ((uns_value << 16) | uns_value); - return "xxspltiw %x0,%2"; -} - [(set_attr "type" "vecperm") - (set_attr "prefixed" "*,*,*,yes")]) - -(define_insn "*xxspltiw_v4si_dup" - [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa,v,wa") - (vec_duplicate:V4SI - (match_operand 1 "const_int_operand" "O,wM,wB,n")))] - "TARGET_XXSPLTIW" -{ - HOST_WIDE_INT sign_value = SIGN_EXTEND_32BIT (INTVAL (operands[1])); - - if (sign_value == 0) - return "xxspltib %x0,0"; - - if (sign_value == -1) - return "xxspltib %x0,255"; - - int r = reg_or_subregno (operands[0]); - if (ALTIVEC_REGNO_P (r) && EASY_VECTOR_15 (sign_value)) - { - operands[2] = GEN_INT (sign_value); - return "vspltisw %0,%2"; - } - - /* The assembler doesn't like negative values. */ - operands[2] = GEN_INT (sign_value & 0xffffffff); - return "xxspltiw %x0,%2"; -} - [(set_attr "type" "vecperm") - (set_attr "prefixed" "*,*,*,yes")]) - -(define_insn "xxspltiw_v4sf_dup" - [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa") - (vec_duplicate:V4SF - (match_operand:SF 1 "const_double_operand" "O,F")))] - "TARGET_XXSPLTIW" -{ - if (operands[1] == CONST0_RTX (SFmode)) - return "xxspltib %x0,0"; - - /* The assembler doesn't like negative values. */ - long value = rs6000_const_f32_to_i32 (operands[1]); - operands[2] = GEN_INT (value & 0xffffffff); - return "xxspltiw %x0,%2"; -} - [(set_attr "type" "vecsimple") - (set_attr "prefixed" "*,yes")]) - -;; Convert vector constant to vec_duplicate. -(define_mode_iterator XXSPLTIW [V8HI V4SI V4SF]) - -(define_split - [(set (match_operand:XXSPLTIW 0 "vsx_register_operand") - (match_operand:XXSPLTIW 1 "xxspltiw_operand"))] - "TARGET_XXSPLTIW" - [(set (match_dup 0) - (vec_duplicate:<MODE> (match_dup 2)))] -{ - operands[2] = CONST_VECTOR_ELT (operands[1], 0); -}) - -;; Generate the XXSPLTIDP instruction to support SFmode and DFmode scalar -;; constants and V2DF vector constants where both elements are the same. The -;; constant has be expressible as a SFmode constant that is not a SFmode -;; denormal value. -(define_mode_iterator XXSPLTIDP [SF DF V2DF]) - -(define_insn_and_split "*xxspltidp_<mode>_internal1" - [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa") - (match_operand:XXSPLTIDP 1 "xxspltidp_operand"))] - "TARGET_XXSPLTIDP" - "#" - "&& 1" - [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand") - (unspec:XXSPLTIDP [(match_dup 2)] UNSPEC_XXSPLTIDP))] -{ - HOST_WIDE_INT value = 0; - - if (!xxspltidp_constant_p (operands[1], <MODE>mode, &value)) - gcc_unreachable (); - - operands[2] = GEN_INT (value); -} - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - -;; Just in case the user issued -mno-xxspltidp, allow the built-in function -;; even if the compiler does not automatically generate XXSPLTIDP. -(define_insn "xxspltidp_<mode>_internal2" - [(set (match_operand:XXSPLTIDP 0 "vsx_register_operand" "=wa") - (unspec:XXSPLTIDP [(match_operand 1 "const_int_operand" "n")] - UNSPEC_XXSPLTIDP))] - "TARGET_POWER10" - "xxspltidp %x0,%1" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c index 22e43d21565..f312550f04d 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c +++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv.c @@ -57,12 +57,7 @@ vector signed int splats3(void) If folding is enabled, the vec_sl tests using vector long long type will generate a lvx instead of a vspltisw+vsld pair. */ -/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 { target { ! has_arch_pwr10 } } } } */ -/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 { target { ! has_arch_pwr10 } } } } */ - -/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 { target { has_arch_pwr10 } } } } */ -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 { target { has_arch_pwr10 } } } } */ -/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 2 { target { has_arch_pwr10 } } } } */ - +/* { dg-final { scan-assembler-times {\mvspltis[bhw]\M|\mxxspltib\M} 7 } } */ +/* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 7 } } */ /* { dg-final { scan-assembler-times {\mlvx\M|\mlxvd2x\M} 0 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c deleted file mode 100644 index 8f6e176f9af..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c +++ /dev/null @@ -1,60 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <math.h> - -/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -double -scalar_double_0 (void) -{ - return 0.0; /* XXSPLTIB or XXLXOR. */ -} - -double -scalar_double_1 (void) -{ - return 1.0; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -double -scalar_double_m0 (void) -{ - return -0.0; /* XXSPLTIDP. */ -} - -double -scalar_double_nan (void) -{ - return __builtin_nan (""); /* XXSPLTIDP. */ -} - -double -scalar_double_inf (void) -{ - return __builtin_inf (); /* XXSPLTIDP. */ -} - -double -scalar_double_m_inf (void) /* XXSPLTIDP. */ -{ - return - __builtin_inf (); -} -#endif - -double -scalar_double_pi (void) -{ - return M_PI; /* PLFD. */ -} - -double -scalar_double_denorm (void) -{ - return 0x1p-149f; /* PLFD. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c deleted file mode 100644 index 72504bdfbbd..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c +++ /dev/null @@ -1,60 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <math.h> - -/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -float -scalar_float_0 (void) -{ - return 0.0f; /* XXSPLTIB or XXLXOR. */ -} - -float -scalar_float_1 (void) -{ - return 1.0f; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -float -scalar_float_m0 (void) -{ - return -0.0f; /* XXSPLTIDP. */ -} - -float -scalar_float_nan (void) -{ - return __builtin_nanf (""); /* XXSPLTIDP. */ -} - -float -scalar_float_inf (void) -{ - return __builtin_inff (); /* XXSPLTIDP. */ -} - -float -scalar_float_m_inf (void) /* XXSPLTIDP. */ -{ - return - __builtin_inff (); -} -#endif - -float -scalar_float_pi (void) -{ - return (float)M_PI; /* XXSPLTIDP. */ -} - -float -scalar_float_denorm (void) -{ - return 0x1p-149f; /* PLFS. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c deleted file mode 100644 index d509459292c..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c +++ /dev/null @@ -1,64 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <math.h> - -/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -vector double -v2df_double_0 (void) -{ - return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */ -} - -vector double -v2df_double_1 (void) -{ - return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -vector double -v2df_double_m0 (void) -{ - return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_nan (void) -{ - return (vector double) { __builtin_nan (""), - __builtin_nan ("") }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_inf (void) -{ - return (vector double) { __builtin_inf (), - __builtin_inf () }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_m_inf (void) -{ - return (vector double) { - __builtin_inf (), - - __builtin_inf () }; /* XXSPLTIDP. */ -} -#endif - -vector double -v2df_double_pi (void) -{ - return (vector double) { M_PI, M_PI }; /* PLFD. */ -} - -vector double -v2df_double_denorm (void) -{ - return (vector double) { (double)0x1p-149f, - (double)0x1p-149f }; /* PLFD. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c deleted file mode 100644 index 06830b02076..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c +++ /dev/null @@ -1,66 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <altivec.h> - -/* Test whether XXSPLTIW is generated for V4SF vector constants. */ - -vector float -v4sf_const_1 (void) -{ - return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_nan (void) -{ - return (vector float) { __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf ("") }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_inf (void) -{ - return (vector float) { __builtin_inff (), - __builtin_inff (), - __builtin_inff (), - __builtin_inff () }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_m0 (void) -{ - return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIW. */ -} - -vector float -v4sf_splats_1 (void) -{ - return vec_splats (1.0f); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_nan (void) -{ - return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_inf (void) -{ - return vec_splats (__builtin_inff ()); /* XXSPLTIW. */ -} - -vector float -v8hi_splats_m0 (void) -{ - return vec_splats (-0.0f); /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 8 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c deleted file mode 100644 index 02d0c6d66a2..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <altivec.h> - -/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure - the power9 support (XXSPLTIB/VEXTSB2W) is not done. */ - -vector int -v4si_const_1 (void) -{ - return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */ -} - -vector int -v4si_const_126 (void) -{ - return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector int -v4si_const_1023 (void) -{ - return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector int -v4si_splats_1 (void) -{ - return vec_splats (1); /* VSLTPISW. */ -} - -vector int -v4si_splats_126 (void) -{ - return vec_splats (126); /* XXSPLTIW. */ -} - -vector int -v8hi_splats_1023 (void) -{ - return vec_splats (1023); /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c deleted file mode 100644 index e6d0fab6d67..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c +++ /dev/null @@ -1,53 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <altivec.h> - -/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure - the power9 support (XXSPLTIB/VUPKLSB) is not done. */ - -vector short -v8hi_const_1 (void) -{ - return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */ -} - -vector short -v8hi_const_126 (void) -{ - return (vector short) { 126, 126, 126, 126, - 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector short -v8hi_const_1023 (void) -{ - return (vector short) { 1023, 1023, 1023, 1023, - 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1 (void) -{ - return vec_splats ((short)1); /* VSLTPISH. */ -} - -vector short -v8hi_splats_126 (void) -{ - return vec_splats ((short)126); /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1023 (void) -{ - return vec_splats ((short)1023); /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c index f49ef91422e..a135279b1d7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c @@ -149,6 +149,8 @@ main (int argc, char *argv []) return 0; } -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */ +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */ + +
next reply other threads:[~2021-07-22 3:09 UTC|newest] Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-07-22 3:09 Michael Meissner [this message] -- strict thread matches above, loose matches on Subject: below -- 2021-07-22 2:45 Michael Meissner 2021-07-22 1:13 Michael Meissner 2021-07-21 22:59 Michael Meissner 2021-07-21 21:44 Michael Meissner
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