[gcc(refs/users/meissner/heads/work062)] Do not allow prefixed loads/stores in PowerPC asm.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:93df1f7c4ed07ed5db522f570a5bfca80998ad30

commit 93df1f7c4ed07ed5db522f570a5bfca80998ad30
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Fri Jul 30 23:59:52 2021 -0400

    Do not allow prefixed loads/stores in PowerPC asm.
    
    The PowerPC has noraml loads and stores and then it has prefixed loads and
    stores.  The prefixed loads and stores have different names and format
    than the normal loads and stores.  This patch adds a new hook that is run
    in the passes before reload to ensure that no prefixed memory is generated
    by optimizations.
    
    This patch contains the PowerPC bits to ensure that prefixed addresses are
    not passed as asm operands.
    
    2021-07-31  Michael Meissner  <meissner@linux.ibm.com>
    gcc/
            PR target/98519
            * config/rs6000/rs6000.c (rs6000_asm_operand_p): New function.
            (TARGET_MD_ASM_OPERAND_P): Override md_asm_operand_p hook.
    
    gcc/testsuite/
            PR target/98519
            * gcc.target/powerpc/pr98519.c: New test.

Diff:
---
 gcc/config/rs6000/rs6000.c                 | 28 ++++++++++++++++++++++++++++
 gcc/testsuite/gcc.target/powerpc/pr98519.c | 20 ++++++++++++++++++++
 2 files changed, 48 insertions(+)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 2de5a96e1b6..73e87c3cbc6 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -1196,6 +1196,8 @@ static bool rs6000_secondary_reload_move (enum rs6000_reg_type,
 					  bool);
 rtl_opt_pass *make_pass_analyze_swaps (gcc::context*);
 
+static bool rs6000_asm_operand_p (rtx, const char *, const char **);
+
 /* Hash table stuff for keeping track of TOC entries.  */
 
 struct GTY((for_user)) toc_hash_struct
@@ -1639,6 +1641,9 @@ static const struct attribute_spec rs6000_attribute_table[] =
 #undef TARGET_LEGITIMATE_ADDRESS_P
 #define TARGET_LEGITIMATE_ADDRESS_P rs6000_legitimate_address_p
 
+#undef TARGET_MD_ASM_OPERAND_P
+#define TARGET_MD_ASM_OPERAND_P rs6000_asm_operand_p
+
 #undef TARGET_MODE_DEPENDENT_ADDRESS_P
 #define TARGET_MODE_DEPENDENT_ADDRESS_P rs6000_mode_dependent_address_p
 
@@ -9921,6 +9926,29 @@ rs6000_offsettable_memref_p (rtx op, machine_mode reg_mode, bool strict)
 					     strict, worst_case);
 }
 
+/* Add additional constraints for asm operands.  We use it to prevent
+   prefixed loads/stores from appearing in normal asm statements.
+
+   At the moment, we just ban all prefixed loads/stores.  If we add a
+   constraint specifically for prefixed loads/stores, we might need to scan the
+   constraint string for that constraint.  */
+
+static bool
+rs6000_asm_operand_p (rtx op,
+		      const char *constraint ATTRIBUTE_UNUSED,
+		      const char **constraints ATTRIBUTE_UNUSED)
+{
+  if (TARGET_PREFIXED && MEM_P (op))
+    {
+      rtx addr = XEXP (op, 0);
+      machine_mode mode = GET_MODE (op);
+      if (address_is_prefixed (addr, mode, NON_PREFIXED_DEFAULT))
+	return false;
+    }
+
+  return true;
+}
+
 /* Determine the reassociation width to be used in reassociate_bb.
    This takes into account how many parallel operations we
    can actually do of a given type, and also the latency.
diff --git a/gcc/testsuite/gcc.target/powerpc/pr98519.c b/gcc/testsuite/gcc.target/powerpc/pr98519.c
new file mode 100644
index 00000000000..25918bac3ed
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr98519.c
@@ -0,0 +1,20 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_prefixed_addr } */
+/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
+
+/* Compile with -mcpu=power10.  The lxsd instruction should not be replaced
+   with a plxsd.  */
+typedef vector double vf64_t;
+
+static double test_f64[16];
+
+vf64_t
+bug (void)
+{
+  vf64_t j0;
+  __asm__("lxsd%X1 %0,%1;" : "=v" (j0) : "m" (test_f64));
+  return j0;
+}
+
+/* { dg-final { scan-assembler     {\mlxsd\M}  } } */
+/* { dg-final { scan-assembler-not {\mplxsd\M} } } */