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From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work062)] Revert patch.
Date: Mon, 2 Aug 2021 03:59:03 +0000 (GMT) [thread overview]
Message-ID: <20210802035903.52D8D385503E@sourceware.org> (raw)
https://gcc.gnu.org/g:b1fd3499d81fa32f20f5205587f65f694ea3e80e
commit b1fd3499d81fa32f20f5205587f65f694ea3e80e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Sun Aug 1 23:58:24 2021 -0400
Revert patch.
2021-07-31 Michael Meissner <meissner@linux.ibm.com>
gcc/
Revert patch.
PR target/98519
* config/rs6000/constraints.md (top level): Adjust comment about
the available unused constraints.
(constraint "m"). New constraint.
* config/rs6000/rs6000.h (TARGET_MEM_CONSTRAINT): Define, making
'k' the new memory cosntraint.
* config/rs6000/rs6000.md (ptrm): Use "k" instead of "m".
(zero_extendqi<mode>2): Likewise.
(zero_extendhi<mode>2): Likewise.
(zero_extendsi<mode>2): Likewise.
(extendhi<mode>2): Likewise.
(signbit<mode>2_dm_mem): Likewise.
(floatdidf2_mem): Likewise.
(floatunsdidf2_mem): Likewise.
(floatdisf2_mem): Likewise.
(floatunsdisf2_mem): Likewise.
(movsi_internal1): Likewise.
(movdi_from_sf_zero_ext): Likewise.
(mov<mode>_internal, QHI iterator): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov<mode>_softfloat): Likewise.
(mov<mode>_hardfloat32): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_64bit_dm): Likewise.
(movtd_64bit_nodm): Likewise.
(mov<mode>_32bit. FMOVE128 iterator): Likewise.
(extenddf<mode>2, IBM128 iterator): Likewise.
(extendtf<mode>2): Likewise.
(reload_<mode>_load): Likewise.
(reload_<RELOAD:mode>_<P:mptrsize>_load): Likewise.
(movdi_internal32): Likewise.
(movdi_internal64): Likewise.
(pltseq_tocsave_<mode>): Likewise.
(probe_stack_<mode>): Likewise.
(stack_protect_setsi): Likewise.
(stack_protect_testsi): Likewise.
(crsave): Likewise.
(stmw): Likewise.
(save_gpregs_<mode>_r11): Likewise.
(save_gpregs_<mode>_r12): Likewise.
(save_gpregs_<mode>_r1): Likewise.
(save_fpregs_<mode>_r11): Likewise.
(save_fpregs_<mode>_r12): Likewise.
(save_fpregs_<mode>_r1): Likewise.
(mtcrfsi): Likewise.
(restore_gpregs_<mode>_r11): Likewise.
(restore_gpregs_<mode>_r12): Likewise.
(restore_gpregs_<mode>_r1): Likewise.
(return_and_restore_gpregs): Likewise.
(return_and_restore_fpregs): Likewise.
(hashst): Likewise.
(hashchk): Likewise.
gcc/testsuite/
Revert patch.
PR target/98519
* gcc.target/powerpc/pr98519.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 +-
gcc/config/rs6000/rs6000.h | 7 --
gcc/config/rs6000/rs6000.md | 148 ++++++++++++++---------------
gcc/testsuite/gcc.target/powerpc/pr98519.c | 20 ----
4 files changed, 75 insertions(+), 110 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index a0a3cdb33a8..561ce9797af 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -17,7 +17,7 @@
;; along with GCC; see the file COPYING3. If not see
;; <http://www.gnu.org/licenses/>.
-;; Available constraint letters: q t u A B C D S T
+;; Available constraint letters: e k q t u A B C D S T
;; Register constraints
@@ -65,14 +65,6 @@
(define_register_constraint "l" "LINK_REGS"
"The link register, @code{lr}.")
-; This defines 'm' as normal memory constraint. This is only possible
-; since the standard memory constraint is re-defined in rs6000.h using
-; the TARGET_MEM_CONSTRAINT macro (to be k).
-(define_memory_constraint "m"
- "Matches the most general non-prefixed memory address, suitable for asm."
- (and (match_code "mem")
- (not (match_operand 0 "prefixed_memory"))))
-
(define_register_constraint "x" "CR0_REGS"
"Condition register field 0, @code{cr0}.")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 14b99fb0edb..4ca6372435d 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -1248,13 +1248,6 @@ enum r6000_reg_class_enum {
extern enum reg_class rs6000_constraints[RS6000_CONSTRAINT_MAX];
-/* This definition replaces the formerly used 'm' constraint with a
- different constraint letter in order to avoid changing semantics of
- the 'm' constraint when accepting new address formats in
- TARGET_LEGITIMATE_ADDRESS_P. The constraint letter defined here
- must not be used in insn definitions or inline assemblies. */
-#define TARGET_MEM_CONSTRAINT 'k'
-
/* The class value for index registers, and the one for base regs. */
#define INDEX_REG_CLASS GENERAL_REGS
#define BASE_REG_CLASS BASE_REGS
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 38f235bbc2c..a84438f8545 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -728,7 +728,7 @@
(define_mode_attr ptrload [(SI "lwz")
(DI "ld")])
-(define_mode_attr ptrm [(SI "k")
+(define_mode_attr ptrm [(SI "m")
(DI "Y")])
(define_mode_attr rreg [(SF "f")
@@ -836,7 +836,7 @@
(define_insn "zero_extendqi<mode>2"
[(set (match_operand:EXTQI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "k,r,Z,v")))]
+ (zero_extend:EXTQI (match_operand:QI 1 "reg_or_mem_operand" "m,r,Z,v")))]
""
"@
lbz%U1%X1 %0,%1
@@ -890,7 +890,7 @@
(define_insn "zero_extendhi<mode>2"
[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,^wa,^v")
- (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "k,r,Z,v")))]
+ (zero_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
""
"@
lhz%U1%X1 %0,%1
@@ -944,7 +944,7 @@
(define_insn "zero_extendsi<mode>2"
[(set (match_operand:EXTSI 0 "gpc_reg_operand" "=r,r,d,wa,wa,r,wa")
- (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "k,r,Z,Z,r,wa,wa")))]
+ (zero_extend:EXTSI (match_operand:SI 1 "reg_or_mem_operand" "m,r,Z,Z,r,wa,wa")))]
""
"@
lwz%U1%X1 %0,%1
@@ -1059,7 +1059,7 @@
(define_insn "*extendhi<mode>2"
[(set (match_operand:EXTHI 0 "gpc_reg_operand" "=r,r,?*v,?*v")
- (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "k,r,Z,v")))]
+ (sign_extend:EXTHI (match_operand:HI 1 "reg_or_mem_operand" "m,r,Z,v")))]
""
"@
lha%U1%X1 %0,%1
@@ -5140,7 +5140,7 @@
;; little endian, we have to load the 2nd double-word to get the sign bit.
(define_insn_and_split "*signbit<mode>2_dm_mem"
[(set (match_operand:DI 0 "gpc_reg_operand" "=b")
- (unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "k")]
+ (unspec:DI [(match_operand:SIGNBIT 1 "memory_operand" "m")]
UNSPEC_SIGNBIT))]
"TARGET_POWERPC64 && TARGET_DIRECT_MOVE"
"#"
@@ -6656,7 +6656,7 @@
(define_insn_and_split "*floatdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
- (float:DF (match_operand:DI 1 "memory_operand" "k,Z")))
+ (float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFID"
"#"
@@ -6685,7 +6685,7 @@
(define_insn_and_split "*floatunsdidf2_mem"
[(set (match_operand:DF 0 "gpc_reg_operand" "=d,wa")
- (unsigned_float:DF (match_operand:DI 1 "memory_operand" "k,Z")))
+ (unsigned_float:DF (match_operand:DI 1 "memory_operand" "m,Z")))
(clobber (match_scratch:DI 2 "=d,wa"))]
"TARGET_HARD_FLOAT && (TARGET_FCFIDU || VECTOR_UNIT_VSX_P (DFmode))"
"#"
@@ -6729,7 +6729,7 @@
(define_insn_and_split "*floatdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
- (float:SF (match_operand:DI 1 "memory_operand" "k,k,Z")))
+ (float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDS"
"#"
@@ -6810,7 +6810,7 @@
(define_insn_and_split "*floatunsdisf2_mem"
[(set (match_operand:SF 0 "gpc_reg_operand" "=f,wa,wa")
- (unsigned_float:SF (match_operand:DI 1 "memory_operand" "k,k,Z")))
+ (unsigned_float:SF (match_operand:DI 1 "memory_operand" "m,m,Z")))
(clobber (match_scratch:DI 2 "=d,d,wa"))]
"TARGET_HARD_FLOAT && TARGET_FCFIDUS"
"#"
@@ -7297,7 +7297,7 @@
[(set (match_operand:SI 0 "nonimmediate_operand"
"=r, r,
r, d, v,
- k, Z, Z,
+ m, Z, Z,
r, r, r, r,
wa, wa, wa, v,
wa, v, v,
@@ -7305,7 +7305,7 @@
r, *h, *h")
(match_operand:SI 1 "input_operand"
"r, U,
- k, Z, Z,
+ m, Z, Z,
r, d, v,
I, L, eI, n,
wa, O, wM, wB,
@@ -7388,11 +7388,11 @@
(define_insn_and_split "movsi_from_sf"
[(set (match_operand:SI 0 "nonimmediate_operand"
- "=r, r, ?*d, ?*v, k,
- k, wY, Z, r, ?*wa,
+ "=r, r, ?*d, ?*v, m,
+ m, wY, Z, r, ?*wa,
wa")
(unspec:SI [(match_operand:SF 1 "input_operand"
- "r, k, Z, Z, r,
+ "r, m, Z, Z, r,
f, v, wa, wa, wa,
r")]
UNSPEC_SI_FROM_SF))
@@ -7454,7 +7454,7 @@
?v, wa")
(zero_extend:DI
(unspec:SI [(match_operand:SF 1 "input_operand"
- "r, k, Z, Z, wa,
+ "r, m, Z, Z, wa,
wa, r")]
UNSPEC_SI_FROM_SF)))
(clobber (match_scratch:V4SF 2
@@ -7586,11 +7586,11 @@
;; MTVSRWZ MF%1 MT%1 NOP
(define_insn "*mov<mode>_internal"
[(set (match_operand:QHI 0 "nonimmediate_operand"
- "=r, r, wa, k, Z, r,
+ "=r, r, wa, m, Z, r,
wa, wa, wa, v, ?v, r,
wa, r, *c*l, *h")
(match_operand:QHI 1 "input_operand"
- "r, k, Z, r, wa, i,
+ "r, m, Z, r, wa, i,
wa, O, wM, wB, wS, wa,
r, *h, r, 0"))]
"gpc_reg_operand (operands[0], <MODE>mode)
@@ -7727,11 +7727,11 @@
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=!r, f, v, wa, k, wY,
- Z, k, wa, !r, f, wa,
+ "=!r, f, v, wa, m, wY,
+ Z, m, wa, !r, f, wa,
!r, *c*l, !r, *h")
(match_operand:SF 1 "input_operand"
- "k, k, wY, Z, f, v,
+ "m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
r, r, *h, 0"))]
"(register_operand (operands[0], SFmode)
@@ -7769,10 +7769,10 @@
;; FMR MR MT%0 MF%1 NOP
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
- "=!r, d, k, Z, ?d, ?r,
+ "=!r, d, m, Z, ?d, ?r,
f, !r, *c*l, !r, *h")
(match_operand:SD 1 "input_operand"
- "k, Z, r, wx, r, d,
+ "m, Z, r, wx, r, d,
f, r, r, *h, 0"))]
"(register_operand (operands[0], SDmode)
|| register_operand (operands[1], SDmode))
@@ -7800,11 +7800,11 @@
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, *c*l, r, r, k, r,
+ "=r, *c*l, r, r, m, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
- "r, r, *h, k, r, I,
+ "r, r, *h, m, r, I,
L, G, Fn, 0"))]
"(gpc_reg_operand (operands[0], <MODE>mode)
@@ -7848,10 +7848,10 @@
;; STXSIWX GPR->VSX VSX->GPR GPR->GPR
(define_insn_and_split "movsf_from_si"
[(set (match_operand:SF 0 "nonimmediate_operand"
- "=!r, f, v, wa, k, Z,
+ "=!r, f, v, wa, m, Z,
Z, wa, ?r, !r")
(unspec:SF [(match_operand:SI 1 "input_operand"
- "k, k, wY, Z, r, f,
+ "m, m, wY, Z, r, f,
wa, r, wa, r")]
UNSPEC_SF_FROM_SI))
(clobber (match_scratch:DI 2
@@ -8028,11 +8028,11 @@
(define_insn "*mov<mode>_hardfloat32"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=k, d, d, <f64_p9>, wY,
+ "=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
Y, r, !r")
(match_operand:FMOVE64 1 "input_operand"
- "d, k, d, wY, <f64_p9>,
+ "d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, Y, r"))]
"! TARGET_POWERPC64 && TARGET_HARD_FLOAT
@@ -8095,12 +8095,12 @@
(define_insn "*mov<mode>_hardfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=k, d, d, <f64_p9>, wY,
+ "=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
YZ, r, !r, *c*l, !r,
*h, r, <f64_dm>")
(match_operand:FMOVE64 1 "input_operand"
- "d, k, d, wY, <f64_p9>,
+ "d, m, d, wY, <f64_p9>,
Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>,
r, YZ, r, r, *h,
0, <f64_dm>, r"))]
@@ -8193,11 +8193,11 @@
(define_insn_and_split "*mov<mode>_64bit_dm"
[(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand"
- "=k, d, d, d, Y,
+ "=m, d, d, d, Y,
r, r, r, r, d")
(match_operand:FMOVE128_FPR 1 "input_operand"
- "d, k, d, <zero_fp>, r,
+ "d, m, d, <zero_fp>, r,
<zero_fp>, Y, r, d, r"))]
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && FLOAT128_2REG_P (<MODE>mode)
@@ -8217,8 +8217,8 @@
(set_attr "num_insns" "2")])
(define_insn_and_split "*movtd_64bit_nodm"
- [(set (match_operand:TD 0 "nonimmediate_operand" "=k,d,d,Y,r,r")
- (match_operand:TD 1 "input_operand" "d,k,d,r,Y,r"))]
+ [(set (match_operand:TD 0 "nonimmediate_operand" "=m,d,d,Y,r,r")
+ (match_operand:TD 1 "input_operand" "d,m,d,r,Y,r"))]
"TARGET_HARD_FLOAT && TARGET_POWERPC64 && !WORDS_BIG_ENDIAN
&& (gpc_reg_operand (operands[0], TDmode)
|| gpc_reg_operand (operands[1], TDmode))"
@@ -8234,8 +8234,8 @@
(set_attr "num_insns" "2,2,2,3,3,2")])
(define_insn_and_split "*mov<mode>_32bit"
- [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=k,d,d,d,Y,r,r")
- (match_operand:FMOVE128_FPR 1 "input_operand" "d,k,d,<zero_fp>,r,<zero_fp>Y,r"))]
+ [(set (match_operand:FMOVE128_FPR 0 "nonimmediate_operand" "=m,d,d,d,Y,r,r")
+ (match_operand:FMOVE128_FPR 1 "input_operand" "d,m,d,<zero_fp>,r,<zero_fp>Y,r"))]
"TARGET_HARD_FLOAT && !TARGET_POWERPC64
&& (FLOAT128_2REG_P (<MODE>mode)
|| int_reg_operand_not_pseudo (operands[0], <MODE>mode)
@@ -8303,7 +8303,7 @@
[(set (match_operand:IBM128 0 "gpc_reg_operand" "=d,d,&d")
(float_extend:IBM128
(match_operand:DF 1 "nonimmediate_operand" "d,m,d")))
- (use (match_operand:DF 2 "nonimmediate_operand" "k,k,d"))]
+ (use (match_operand:DF 2 "nonimmediate_operand" "m,m,d"))]
"!TARGET_VSX && TARGET_HARD_FLOAT
&& TARGET_LONG_DOUBLE_128 && FLOAT128_IBM_P (<MODE>mode)"
"#"
@@ -8882,7 +8882,7 @@
;; Reload patterns to support gpr load/store with misaligned mem.
;; and multiple gpr load/store at offset >= 0xfffc
(define_expand "reload_<mode>_store"
- [(parallel [(match_operand 0 "memory_operand" "=k")
+ [(parallel [(match_operand 0 "memory_operand" "=m")
(match_operand 1 "gpc_reg_operand" "r")
(match_operand:GPR 2 "register_operand" "=&b")])]
""
@@ -8893,7 +8893,7 @@
(define_expand "reload_<mode>_load"
[(parallel [(match_operand 0 "gpc_reg_operand" "=r")
- (match_operand 1 "memory_operand" "k")
+ (match_operand 1 "memory_operand" "m")
(match_operand:GPR 2 "register_operand" "=b")])]
""
{
@@ -8907,7 +8907,7 @@
;; for vector registers and reg+reg or (reg+reg)&(-16) addressing to just an
;; index register for gpr registers.
(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_store"
- [(parallel [(match_operand:RELOAD 0 "memory_operand" "k")
+ [(parallel [(match_operand:RELOAD 0 "memory_operand" "m")
(match_operand:RELOAD 1 "gpc_reg_operand" "wa")
(match_operand:P 2 "register_operand" "=b")])]
"<P:tptrsize>"
@@ -8918,7 +8918,7 @@
(define_expand "reload_<RELOAD:mode>_<P:mptrsize>_load"
[(parallel [(match_operand:RELOAD 0 "gpc_reg_operand" "wa")
- (match_operand:RELOAD 1 "memory_operand" "k")
+ (match_operand:RELOAD 1 "memory_operand" "m")
(match_operand:P 2 "register_operand" "=b")])]
"<P:tptrsize>"
{
@@ -9190,12 +9190,12 @@
(define_insn "*movdi_internal32"
[(set (match_operand:DI 0 "nonimmediate_operand"
- "=Y, r, r, k, ^d, ^d,
+ "=Y, r, r, m, ^d, ^d,
r, wY, Z, ^v, $v, ^wa,
wa, wa, v, wa, *i, v,
v")
(match_operand:DI 1 "input_operand"
- "r, Y, r, ^d, k, ^d,
+ "r, Y, r, ^d, m, ^d,
IJKnF, ^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM, wS,
wB"))]
@@ -9281,7 +9281,7 @@
[(set (match_operand:DI 0 "nonimmediate_operand"
"=YZ, r, r,
r, r, r, r,
- k, ^d, ^d,
+ m, ^d, ^d,
wY, Z, $v, $v, ^wa,
wa, wa, v, wa, wa,
v, v,
@@ -9290,7 +9290,7 @@
(match_operand:DI 1 "input_operand"
"r, YZ, r,
I, L, eI, nF,
- ^d, k, ^d,
+ ^d, m, ^d,
^v, $v, wY, Z, ^wa,
Oj, wM, OjwM, Oj, wM,
wS, wB,
@@ -10777,7 +10777,7 @@
"la %0,%2@l(%1)")
(define_insn "*pltseq_tocsave_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=k")
+ [(set (match_operand:P 0 "memory_operand" "=m")
(unspec:P [(match_operand:P 1 "gpc_reg_operand" "b")
(match_operand:P 2 "symbol_ref_operand" "s")
(match_operand:P 3 "" "")]
@@ -11538,7 +11538,7 @@
})
(define_insn "probe_stack_<mode>"
- [(set (match_operand:P 0 "memory_operand" "=k")
+ [(set (match_operand:P 0 "memory_operand" "=m")
(unspec:P [(const_int 0)] UNSPEC_PROBE_STACK))]
""
{
@@ -11926,8 +11926,8 @@
})
(define_insn "stack_protect_setsi"
- [(set (match_operand:SI 0 "memory_operand" "=k")
- (unspec:SI [(match_operand:SI 1 "memory_operand" "k")] UNSPEC_SP_SET))
+ [(set (match_operand:SI 0 "memory_operand" "=m")
+ (unspec:SI [(match_operand:SI 1 "memory_operand" "m")] UNSPEC_SP_SET))
(set (match_scratch:SI 2 "=&r") (const_int 0))]
"TARGET_32BIT"
"lwz%U1%X1 %2,%1\;stw%U0%X0 %2,%0\;li %2,0"
@@ -11999,8 +11999,8 @@
(define_insn "stack_protect_testsi"
[(set (match_operand:CCEQ 0 "cc_reg_operand" "=x,?y")
- (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "k,k")
- (match_operand:SI 2 "memory_operand" "k,k")]
+ (unspec:CCEQ [(match_operand:SI 1 "memory_operand" "m,m")
+ (match_operand:SI 2 "memory_operand" "m,m")]
UNSPEC_SP_TEST))
(set (match_scratch:SI 4 "=r,r") (const_int 0))
(clobber (match_scratch:SI 3 "=&r,&r"))]
@@ -13399,7 +13399,7 @@
(define_insn "*crsave"
[(match_parallel 0 "crsave_operation"
- [(set (match_operand:SI 1 "memory_operand" "=k")
+ [(set (match_operand:SI 1 "memory_operand" "=m")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
""
"stw %2,%1"
@@ -13407,7 +13407,7 @@
(define_insn "*stmw"
[(match_parallel 0 "stmw_operation"
- [(set (match_operand:SI 1 "memory_operand" "=k")
+ [(set (match_operand:SI 1 "memory_operand" "=m")
(match_operand:SI 2 "gpc_reg_operand" "r"))])]
"TARGET_MULTIPLE"
"stmw %2,%1"
@@ -13435,7 +13435,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
- (set (match_operand:P 2 "memory_operand" "=k")
+ (set (match_operand:P 2 "memory_operand" "=m")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13446,7 +13446,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
- (set (match_operand:P 2 "memory_operand" "=k")
+ (set (match_operand:P 2 "memory_operand" "=m")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13457,7 +13457,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
- (set (match_operand:P 2 "memory_operand" "=k")
+ (set (match_operand:P 2 "memory_operand" "=m")
(match_operand:P 3 "gpc_reg_operand" "r"))])]
""
"bl %1"
@@ -13468,7 +13468,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
- (set (match_operand:DF 2 "memory_operand" "=k")
+ (set (match_operand:DF 2 "memory_operand" "=m")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13479,7 +13479,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
- (set (match_operand:DF 2 "memory_operand" "=k")
+ (set (match_operand:DF 2 "memory_operand" "=m")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13490,7 +13490,7 @@
[(clobber (reg:P LR_REGNO))
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
- (set (match_operand:DF 2 "memory_operand" "=k")
+ (set (match_operand:DF 2 "memory_operand" "=m")
(match_operand:DF 3 "gpc_reg_operand" "d"))])]
""
"bl %1"
@@ -13576,7 +13576,7 @@
(define_insn "*lmw"
[(match_parallel 0 "lmw_operation"
[(set (match_operand:SI 1 "gpc_reg_operand" "=r")
- (match_operand:SI 2 "memory_operand" "k"))])]
+ (match_operand:SI 2 "memory_operand" "m"))])]
"TARGET_MULTIPLE"
"lmw %1,%2"
[(set_attr "type" "load")
@@ -13607,7 +13607,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "k"))])]
+ (match_operand:P 3 "memory_operand" "m"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13618,7 +13618,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "k"))])]
+ (match_operand:P 3 "memory_operand" "m"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13629,7 +13629,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "k"))])]
+ (match_operand:P 3 "memory_operand" "m"))])]
""
"bl %1"
[(set_attr "type" "branch")])
@@ -13641,7 +13641,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "k"))])]
+ (match_operand:P 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13653,7 +13653,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "k"))])]
+ (match_operand:P 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13665,7 +13665,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:P 2 "gpc_reg_operand" "=r")
- (match_operand:P 3 "memory_operand" "k"))])]
+ (match_operand:P 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13677,7 +13677,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "k"))])]
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13689,7 +13689,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 12))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "k"))])]
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13701,7 +13701,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "k"))])]
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13712,7 +13712,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 11))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "k"))])]
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -13723,7 +13723,7 @@
(use (match_operand:P 1 "symbol_ref_operand" "s"))
(use (reg:P 1))
(set (match_operand:DF 2 "gpc_reg_operand" "=d")
- (match_operand:DF 3 "memory_operand" "k"))])]
+ (match_operand:DF 3 "memory_operand" "m"))])]
""
"b %1"
[(set_attr "type" "branch")])
@@ -15184,7 +15184,7 @@
;; ROP mitigation instructions.
(define_insn "hashst"
- [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=k")
+ [(set (match_operand:DI 0 "simple_offsettable_mem_operand" "=m")
(unspec_volatile:DI [(match_operand:DI 1 "int_reg_operand" "r")]
UNSPEC_HASHST))]
"TARGET_POWER10 && rs6000_rop_protect"
@@ -15198,7 +15198,7 @@
(define_insn "hashchk"
[(unspec_volatile [(match_operand:DI 0 "int_reg_operand" "r")
- (match_operand:DI 1 "simple_offsettable_mem_operand" "k")]
+ (match_operand:DI 1 "simple_offsettable_mem_operand" "m")]
UNSPEC_HASHCHK)]
"TARGET_POWER10 && rs6000_rop_protect"
{
diff --git a/gcc/testsuite/gcc.target/powerpc/pr98519.c b/gcc/testsuite/gcc.target/powerpc/pr98519.c
deleted file mode 100644
index 25918bac3ed..00000000000
--- a/gcc/testsuite/gcc.target/powerpc/pr98519.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* { dg-do compile } */
-/* { dg-require-effective-target powerpc_prefixed_addr } */
-/* { dg-options "-O2 -mdejagnu-cpu=power10" } */
-
-/* Compile with -mcpu=power10. The lxsd instruction should not be replaced
- with a plxsd. */
-typedef vector double vf64_t;
-
-static double test_f64[16];
-
-vf64_t
-bug (void)
-{
- vf64_t j0;
- __asm__("lxsd%X1 %0,%1;" : "=v" (j0) : "m" (test_f64));
- return j0;
-}
-
-/* { dg-final { scan-assembler {\mlxsd\M} } } */
-/* { dg-final { scan-assembler-not {\mplxsd\M} } } */
next reply other threads:[~2021-08-02 3:59 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-08-02 3:59 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-07-31 3:36 Michael Meissner
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