[gcc(refs/users/meissner/heads/work064)] Update ChangeLog.meissner.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:b7c447db268cab20da60d008daee8ad66c8fc587

commit b7c447db268cab20da60d008daee8ad66c8fc587
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Thu Aug 12 22:07:10 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-08-12  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-08-12  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 112 +++++++++++++++++++++++++++++++++++++++
 gcc/testsuite/ChangeLog.meissner |  33 ++++++++++++
 2 files changed, 145 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index e821b156bf1..47703712bfc 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,115 @@
+work064.patch005:
+2021-08-12  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/constraints.md (eF): New constraint.
+	* config/rs6000/predicates.md (easy_fp_constant): If we can load
+	the scalar constant with XXSPLTIDP, the floating point constant is
+	easy.
+	(xxspltidp_operand): New predicate.
+	(easy_vector_constant): If we can generate XXSPLTIDP, mark the
+	vector constant as easy.
+	* config/rs6000/rs6000-cpus.def (OTHER_POWER10_MASKS): Add
+	-mxxspltidp support.
+	(POWERPC_MASKS): Add -mxxspltidp support.
+	* config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New
+	declaration.
+	* config/rs6000/rs6000.c (const_vector_element_all_same): New
+	function.
+	(xxspltidp_constant_p): New function.
+	(output_vec_const_move): Add support for XXSPLTIDP.
+	(rs6000_opt_masks): Add -mxxspltidp support.
+	(rs6000_emit_xxspltidp_v2df): Change function to implement the
+	XXSPLTIDP instruction.
+	* config/rs6000/rs6000.h (TARGET_XXSPLTIDP): New macro.
+	* config/rs6000/rs6000.md (movsf_hardfloat): Add XXSPLTIDP
+	support.
+	(mov<mode>_hardfloat32, FMOVE64 iterator): Add XXSPLTIDP support.
+	(mov<mode>_hardfloat64, FMOVE64 iterator): Add XXSPLTIDP support.
+	* config/rs6000/rs6000.opt (-mxxspltidp): New switch.
+	* config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename UNSPEC_XXSPLTID
+	to UNSPEC_XXSPLTIDP to match the instruction.
+	(xxspltidp_v2df): Use 'use' for the expand arguments, instead of
+	writing out an insn.
+	(xxspltidp_v2df_inst): Delete.
+	(XXSPLTIDP): New mode iterator.
+	(xxspltidp_<mode>_internal1): New define_insn_and_split.
+	(xxspltidp_<mode>_internal2): New define_insn.
+
+work064.patch004:
+2021-07-21  Michael Meissner  <meissner@linux.ibm.com>
+
+	* config/rs6000/predicates.md (xxspltiw_operand): New predicate.
+	(easy_vector_constant): If we can use XXSPLTIW, the vector
+	constant is easy.
+	* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
+	XXSPLTIW, don't generate a XXSPLTIB and an extend instruction.
+	(output_vec_const_move): Add support for loading up vector
+	constants with XXSPLTIW.
+	* config/rs6000/rs6000.h (TARGET_XXSPLTIW): New macro.
+	(SIGN_EXTEND_8BIT): New macro.
+	(SIGN_EXTEND_16BIT): New macro.
+	(SIGN_EXTEND_32BIT): New macro.
+	* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
+	* config/rs6000/vsx.md (UNSPEC_XXSPLTIW): Delete.
+	(xxspltiw_v8hi): New insn.
+	(xxspltiw_v4si): Rewrite to generate a vector constant.
+	(xxspltiw_v4sf): Rewrite to generate a vector constant.
+	(xxspltiw_v4si_inst): Delete.
+	(xxspltiw_v4sf_inst): Delete.
+	(xxspltiw_v8hi_dup): New insn.
+	(xxspltiw_v4si_dup): New insn.
+	(xxspltiw_v4sf_dup): New insn.
+	(XXSPLTIW): New mode iterator.
+	(XXSPLTIW splitter): New insn splitter for XXSPLTIW.
+
+work064.patch003:
+2021-08-12  Michael Meissner  <meissner@linux.ibm.com>
+	* config/rs6000/altivec.md (UNSPEC_XXEVAL): Move to vsx.md.
+	(UNSPEC_XXSPLTIW): Move to vsx.md.
+	(UNSPEC_XXSPLTID): Move to vsx.md.
+	(UNSPEC_XXSPLTI32DX): Move to vsx.md.
+	(UNSPEC_XXBLEND): Move to vsx.md.
+	(UNSPEC_XXPERMX): Move to vsx.md.
+	(VM3): Move to vsx.md.
+	(VM3_char): Move to vsx.md.
+	(xxspltiw_v4si): Move to vsx.md.
+	(xxspltiw_v4sf): Move to vsx.md.
+	(xxspltiw_v4sf_inst): Move to vsx.md.
+	(xxspltidp_v2df): Move to vsx.md.
+	(xxspltidp_v2df_inst): Move to vsx.md.
+	(xxsplti32dx_v4si_inst): Move to vsx.md.
+	(xxsplti32dx_v4sf): Move to vsx.md.
+	(xxsplti32dx_v4sf_inst): Move to vsx.md.
+	(xxblend_<mode>): Move to vsx.md.
+	(xxpermx): Move to vsx.md.
+	(xxpermx_inst): Move to vsx.md.
+	* config/rs6000/vsx.md (UNSPEC_XXEVAL): Move from altivec.md.
+	(UNSPEC_XXSPLTIW): Move from altivec.md.
+	(UNSPEC_XXSPLTID): Move from altivec.md.
+	(UNSPEC_XXSPLTI32DX): Move from altivec.md.
+	(UNSPEC_XXBLEND): Move from altivec.md.
+	(UNSPEC_XXPERMX): Move from altivec.md.
+	(VM3): Move from altivec.md.
+	(VM3_char): Move from altivec.md.
+	(xxspltiw_v4si): Move from altivec.md.
+	(xxspltiw_v4sf): Move from altivec.md.
+	(xxspltiw_v4sf_inst): Move from altivec.md.
+	(xxspltidp_v2df): Move from altivec.md.
+	(xxspltidp_v2df_inst): Move from altivec.md.
+	(xxsplti32dx_v4si_inst): Move from altivec.md.
+	(xxsplti32dx_v4sf): Move from altivec.md.
+	(xxsplti32dx_v4sf_inst): Move from altivec.md.
+	(xxblend_<mode>): Move from altivec.md.
+	(xxpermx): Move from altivec.md.
+	(xxpermx_inst): Move from altivec.md.
+
+work064.patch002:
+2021-08-12  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/99921
+	* config/rs6000/altivec.md (xxeval): Use register_predicate
+	instead of altivec_register_predicate.
+
 2021-08-12   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index e821b156bf1..0992cbecf28 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,36 @@
+work064.patch005:
+2021-08-12  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/vec-splat-constant-sf.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-df.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v2df.c: New test.
+
+work064.patch004:
+2021-07-21  Michael Meissner  <meissner@linux.ibm.com>
+
+	* gcc.target/powerpc/pr86731-fwrapv.c: Update insn counts on
+	power10.
+	* gcc.target/powerpc/vec-splati-runnable.c: Update insn counts.
+	* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
+	* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
+
+work064.patch001:
+2021-08-12  Michael Meissner  <meissner@linux.ibm.com>
+
+	PR target/94630
+	* gcc.target/powerpc/pr70117.c: Specify that we need the long double
+	type to be IBM 128-bit.  Remove the code to use __ibm128.
+	* c-c++-common/dfp/convert-bfp-11.c: Specify that we need the long
+	double type to be IBM 128-bit.  Run the test at -O2 optimization.
+	* lib/target-supports.exp (add_options_for_long_double_ibm128): New
+	function.
+	(check_effective_target_long_double_ibm128): New function.
+	(add_options_for_long_double_ieee128): New function.
+	(check_effective_target_long_double_ieee128): New function.
+	(add_options_for_long_double_64bit): New function.
+	(check_effective_target_long_double_64bit): New function.
+
 2021-08-12   Michael Meissner  <meissner@linux.ibm.com>
 
 	Clone branch