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From: Richard Earnshaw <rearnsha@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r11-8882] arm: Fix typos for reorder assembler architecture directives [PR101723] Date: Wed, 18 Aug 2021 15:23:24 +0000 (GMT) [thread overview] Message-ID: <20210818152324.4C7703858018@sourceware.org> (raw) https://gcc.gnu.org/g:39bb64e79a280fa773c8dcd79b992745e8c1b738 commit r11-8882-g39bb64e79a280fa773c8dcd79b992745e8c1b738 Author: Christophe Lyon <christophe.lyon@foss.st.com> Date: Fri Aug 6 14:06:44 2021 +0000 arm: Fix typos for reorder assembler architecture directives [PR101723] Two tests had typos preventing them from passing, committed as obvious. 2021-08-06 Christophe Lyon <christophe.lyon@foss.st.com> gcc/testsuite/ PR target/101723 * gcc.target/arm/attr-neon3.c: Fix typo. * gcc.target/arm/pragma_fpu_attribute_2.c: Fix typo. (cherry picked from commit a22b3e022c2b45047a28d901042888eb77620499) Diff: --- gcc/testsuite/gcc.target/arm/attr-neon3.c | 2 +- gcc/testsuite/gcc.target/arm/pragma_fpu_attribute_2.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/arm/attr-neon3.c b/gcc/testsuite/gcc.target/arm/attr-neon3.c index 0fbce6e4cd4..b6171e72d89 100644 --- a/gcc/testsuite/gcc.target/arm/attr-neon3.c +++ b/gcc/testsuite/gcc.target/arm/attr-neon3.c @@ -33,7 +33,7 @@ my (float32x2_t __a, float32x2_t __b) ** | ** vld1.64 {d[0-9]+}, \[r[0-9]+:64\]! ** vld1.64 {d[0-9]+}, \[r[0-9]+:64\] -** } +** ) ** ... ** bx lr */ diff --git a/gcc/testsuite/gcc.target/arm/pragma_fpu_attribute_2.c b/gcc/testsuite/gcc.target/arm/pragma_fpu_attribute_2.c index 3d33b04b787..398d8fff35c 100644 --- a/gcc/testsuite/gcc.target/arm/pragma_fpu_attribute_2.c +++ b/gcc/testsuite/gcc.target/arm/pragma_fpu_attribute_2.c @@ -28,5 +28,5 @@ uint32_t restored () /* We can't tell exactly how many times the following tests will match because command-line options may cause additional instances to be generated, but each must be present at least once. */ -/* { dg-final { scan-assembler-times {\.fpu\s+vfpv4\n} } } */ -/* { dg-final { scan-assembler-times {\.fpu\s+vfpv3-d16\n} } } */ +/* { dg-final { scan-assembler {\.fpu\s+vfpv4\n} } } */ +/* { dg-final { scan-assembler {\.fpu\s+vfpv3-d16\n} } } */
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