From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 10B3D3858C2C; Wed, 25 Aug 2021 01:16:07 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 10B3D3858C2C Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work066)] Update ChangeLog.meissner. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work066 X-Git-Oldrev: 14a1c6fb85f8824bf1a0cf18a2034b461ce0669e X-Git-Newrev: b327026029bf6ba347583d610113110a5a7de177 Message-Id: <20210825011607.10B3D3858C2C@sourceware.org> Date: Wed, 25 Aug 2021 01:16:07 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Aug 2021 01:16:07 -0000 https://gcc.gnu.org/g:b327026029bf6ba347583d610113110a5a7de177 commit b327026029bf6ba347583d610113110a5a7de177 Author: Michael Meissner Date: Tue Aug 24 21:15:40 2021 -0400 Update ChangeLog.meissner. gcc/ 2021-08-24 Michael Meissner * ChangeLog.meissner: Update. gcc/testsuite/ 2021-08-24 Michael Meissner * ChangeLog.meissner: Update. Diff: --- gcc/ChangeLog.meissner | 92 ++++++++++++++++++++++++++++++++++++++++ gcc/testsuite/ChangeLog.meissner | 37 ++++++++++++++++ 2 files changed, 129 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 0190e13c736..fc88d8119c1 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,95 @@ +work066.patch05: +2021-08-24 Michael Meissner + + * config/rs6000/constraints.md (eW): New constraint. + * config/rs6000/predicates.md (xxspltiw_operand): New predicate. + (easy_vector_constant): If we can use XXSPLTIW, the vector + constant is easy. + * config/rs6000/rs6000-protos.h (xxspltiw_constant_p): New + declaration. + * config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate + XXSPLTIW, don't generate a XXSPLTIB and an extend instruction. + (const_vector_all_elements_equal_p): New function. + (xxspltiw_constant_p): New function. + (output_vec_const_move): Add support for loading up vector + constants with XXSPLTIW. + (prefixed_permute_p): Recognize xxspltiw instructions as + prefixed. + * config/rs6000/rs6000.opt (-mxxspltiw): New debug switch. + * config/rs6000/vsx.md (vsx_mov_64bit): Add support for + constants loaded with XXSPLTIW. + (vsx_mov_32bit): Likewise. + (vsx_splat_v8hi_xxspltiw): New insn. + (vsx_splat_v4si_xxspltiw): New insn. + (vsx_splat_v4sf_xxspltiw): New insn. + +work066.patch04: +2021-08-24 Michael Meissner + + * config/rs6000/constraints.md (eQ): New constraint. + * config/rs6000/predicates.md (easy_fp_constant): If we can use + LXVKQ, it is an easy floating point constant. + (lxvkq_operand): New predicate. + * config/rs6000/rs6000-protos.h (lxvkq_constant_p): New + declaration. + * config/rs6000/rs6000.c (lxvkq_constant_p): New function. + (output_vec_const_move): Add support for LXVKQ. + (rs6000_output_move_128bit): Likewise. + * config/rs6000/rs6000.opt (-mlxvkq): New debug option. + * config/rs6000/vsx.md (vsx_mov_64bit): Add support for + LXVKQ. + (vsx_mov_32bit): Likewise. + +work066.patch03: +2021-08-18 Michael Meissner + + * config/rs6000/constraints.md (eF): New constraint. + * config/rs6000/predicates.md (easy_fp_constant): If we can load + the scalar constant with XXSPLTIDP, the floating point constant is + easy. + (xxspltidp_operand): New predicate. + (easy_vector_constant): If we can generate XXSPLTIDP, mark the + vector constant as easy. + * config/rs6000/rs6000-protos.h (xxspltidp_constant_p): New + declaration. + (prefixed_permute_p): Likewise. + * config/rs6000/rs6000.c (xxspltidp_constant_p): New function. + (output_vec_const_move): Add support for XXSPLTIDP. + (prefixed_permute_p): New function. + * config/rs6000/rs6000.md (prefixed attribute): Add support for + permute prefixed instructions. + (movsf_hardfloat): Add XXSPLTIDP support. + (mov_hardfloat32, FMOVE64 iterator): Likewise. + (mov_hardfloat64, FMOVE64 iterator): Likewise. + * config/rs6000/rs6000.opt (-mxxspltidp): New switch. + * config/rs6000/vsx.md (vsx_move_64bit): Add XXSPLTIDP + support. + (vsx_move_32bit): Likewise. + (vsx_splat_v2df_xxspltidp): New insn. + (XXSPLTIDP): New mode iterator. + (xxspltidp__internal): New insn and splits. + (xxspltidp__inst): Replace xxspltidp_v2df_inst with an + iterated form that also does SFmode, and DFmode. + +work066.patch02: +2021-08-24 Michael Meissner + + * config/rs6000/vsx.md (UNSPEC_XXSPLTIDP): Rename from + UNSPEC_XXSPLTID. + (xxspltiw_v4si): Use vecperm type attribute. + (xxspltiw_v4si_inst): Use vecperm type attribute. + (xxspltiw_v4sf_inst): Likewise. + (xxspltidp_v2df): Use vecperm type attribute. Use + UUNSPEC_XXSPLTIDP instead of UNSPEC_XXSPLTID. + (xxspltidp_v2df_inst): Likewise. + (xxsplti32dx_v4si): Use vecperm type attribute. + (xxsplti32dx_v4si_inst): Likewise. + (xxsplti32dx_v4sf_inst): Likewise. + (xxblend_): Likewise. + (xxpermx): Likewise. + (xxpermx_inst): Likewise. + (xxeval): Likewise. + 2021-08-24 Michael Meissner Clone branch diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner index 0190e13c736..e3b8d917531 100644 --- a/gcc/testsuite/ChangeLog.meissner +++ b/gcc/testsuite/ChangeLog.meissner @@ -1,3 +1,40 @@ +work066.patch05: +2021-08-24 Michael Meissner + + * gcc.target/powerpc/vec-splat-constant-v16qi.c: New test. + * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. + * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. + * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. + * gcc.target/powerpc/vec-splati-runnable.c: Update insn counts. + +work066.patch04: +2021-08-24 Michael Meissner + + * gcc.target/powerpc/float128-constant.c: New test. + +work066.patch03: +2021-08-18 Michael Meissner + + * gcc.target/powerpc/vec-splat-constant-sf.c: New test. + * gcc.target/powerpc/vec-splat-constant-df.c: New test. + * gcc.target/powerpc/vec-splat-constant-v2df.c: New test. + +work066.patch01: +2021-08-24 Michael Meissner + + PR target/94630 + * gcc.target/powerpc/pr70117.c: Specify that we need the long double + type to be IBM 128-bit. Remove the code to use __ibm128. + * c-c++-common/dfp/convert-bfp-11.c: Specify that we need the long + double type to be IBM 128-bit. Run the test at -O2 optimization. + * lib/target-supports.exp (add_options_for_long_double_ibm128): New + function. + (check_effective_target_long_double_ibm128): New function. + (add_options_for_long_double_ieee128): New function. + (check_effective_target_long_double_ieee128): New function. + (add_options_for_long_double_64bit): New function. + (check_effective_target_long_double_64bit): New function. + 2021-08-24 Michael Meissner Clone branch