From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7863) id 10A373858D34; Tue, 31 Aug 2021 01:39:27 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 10A373858D34 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: YunQiang Su To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-3240] MIPS: use mips_isa enum instead hardcoded numbers X-Act-Checkin: gcc X-Git-Author: YunQiang Su X-Git-Refname: refs/heads/master X-Git-Oldrev: f4b41701382885fc6219045bed207ec645fded2e X-Git-Newrev: 4ecfc7e3debac53a30558d7ae33e8cdfdf351466 Message-Id: <20210831013927.10A373858D34@sourceware.org> Date: Tue, 31 Aug 2021 01:39:27 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 31 Aug 2021 01:39:27 -0000 https://gcc.gnu.org/g:4ecfc7e3debac53a30558d7ae33e8cdfdf351466 commit r12-3240-g4ecfc7e3debac53a30558d7ae33e8cdfdf351466 Author: YunQiang Su Date: Sat Aug 28 07:28:55 2021 -0400 MIPS: use mips_isa enum instead hardcoded numbers Currently mips-cpu.defs, mips.h, netbsd.h and config.gcc are using hardcoded numbers for isa level. Let's replace them with more readable enum mips_isa. gcc/ChangeLog: * config/mips/mips.h (struct mips_cpu_info): define enum mips_isa; use enum instead of int for 'isa' member. * config.gcc, config/mips/mips.c, config/mips/mips-cpus.def, config/mips/netbsd.h: replace hardcoded numbers with enum. Diff: --- gcc/config.gcc | 62 ++++++------ gcc/config/mips/mips-cpus.def | 228 +++++++++++++++++++++--------------------- gcc/config/mips/mips.c | 5 +- gcc/config/mips/mips.h | 84 ++++++++++------ gcc/config/mips/netbsd.h | 5 +- 5 files changed, 203 insertions(+), 181 deletions(-) diff --git a/gcc/config.gcc b/gcc/config.gcc index 0c91be6f35b..0eba332bd45 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -2512,7 +2512,7 @@ mips*-img-linux*) tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h mips/mti-linux.h" extra_options="${extra_options} linux-android.opt" tmake_file="${tmake_file} mips/t-img-linux" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r6" with_arch_64="mips64r6" gnu_ld=yes @@ -2522,7 +2522,7 @@ mips*-mti-linux*) tm_file="dbxelf.h elfos.h gnu-user.h linux.h linux-android.h glibc-stdint.h ${tm_file} mips/gnu-user.h mips/linux.h mips/linux-common.h mips/mti-linux.h" extra_options="${extra_options} linux-android.opt" tmake_file="${tmake_file} mips/t-mti-linux" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r2" with_arch_64="mips64r2" gnu_ld=yes @@ -2592,14 +2592,14 @@ mips*-*-linux*) # Linux MIPS, either endian. mips*-mti-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h mips/sde.h mips/mti-elf.h" tmake_file="mips/t-mti-elf" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r2" with_arch_64="mips64r2" ;; mips*-img-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h mips/sde.h mips/mti-elf.h" tmake_file="mips/t-img-elf" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 MIPS_ABI_DEFAULT=ABI_32" with_arch_32="mips32r6" with_arch_64="mips64r6" ;; @@ -2624,22 +2624,22 @@ mips*-sde-elf*) esac case ${target} in mipsisa32r6*) - tm_defines="MIPS_ISA_DEFAULT=37 MIPS_ABI_DEFAULT=ABI_32" + tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6 MIPS_ABI_DEFAULT=ABI_32" ;; mipsisa32r2*) - tm_defines="MIPS_ISA_DEFAULT=33 MIPS_ABI_DEFAULT=ABI_32" + tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2 MIPS_ABI_DEFAULT=ABI_32" ;; mipsisa32*) - tm_defines="MIPS_ISA_DEFAULT=32 MIPS_ABI_DEFAULT=ABI_32" + tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32 MIPS_ABI_DEFAULT=ABI_32" ;; mipsisa64r6*) - tm_defines="MIPS_ISA_DEFAULT=69 MIPS_ABI_DEFAULT=ABI_N32" + tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R6 MIPS_ABI_DEFAULT=ABI_N32" ;; mipsisa64r2*) - tm_defines="MIPS_ISA_DEFAULT=65 MIPS_ABI_DEFAULT=ABI_N32" + tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2 MIPS_ABI_DEFAULT=ABI_N32" ;; mipsisa64*) - tm_defines="MIPS_ISA_DEFAULT=64 MIPS_ABI_DEFAULT=ABI_N32" + tm_defines="MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64 MIPS_ABI_DEFAULT=ABI_N32" ;; esac ;; @@ -2653,22 +2653,22 @@ mipsisa64r6-*-elf* | mipsisa64r6el-*-elf*) tmake_file="mips/t-isa3264" case ${target} in mipsisa32r6*) - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=37" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6" ;; mipsisa32r2*) - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=33" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2" ;; mipsisa32*) - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=32" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32" ;; mipsisa64r6*) - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=69" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R6" ;; mipsisa64r2*) - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=65" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2" ;; mipsisa64*) - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64" ;; esac case ${target} in @@ -2688,12 +2688,12 @@ mipsisa64r6-*-elf* | mipsisa64r6el-*-elf*) mipsisa64sr71k-*-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h" tmake_file=mips/t-sr71k - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"sr71000\\\" MIPS_ABI_DEFAULT=ABI_EABI" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64 MIPS_CPU_STRING_DEFAULT=\\\"sr71000\\\" MIPS_ABI_DEFAULT=ABI_EABI" ;; mipsisa64sb1-*-elf* | mipsisa64sb1el-*-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h" tmake_file="mips/t-elf mips/t-sb1" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=64 MIPS_CPU_STRING_DEFAULT=\\\"sb1\\\" MIPS_ABI_DEFAULT=ABI_O64" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64 MIPS_CPU_STRING_DEFAULT=\\\"sb1\\\" MIPS_ABI_DEFAULT=ABI_O64" ;; mips-*-elf* | mipsel-*-elf* | mipsr5900-*-elf* | mipsr5900el-*-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h" @@ -2702,12 +2702,12 @@ mips-*-elf* | mipsel-*-elf* | mipsr5900-*-elf* | mipsr5900el-*-elf*) mips64r5900-*-elf* | mips64r5900el-*-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/n32-elf.h" tmake_file="mips/t-elf" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_N32" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS3 MIPS_ABI_DEFAULT=ABI_N32" ;; mips64-*-elf* | mips64el-*-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h" tmake_file="mips/t-elf" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS3 MIPS_ABI_DEFAULT=ABI_O64" ;; mips64vr-*-elf* | mips64vrel-*-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/vr.h mips/elf.h" @@ -2717,7 +2717,7 @@ mips64vr-*-elf* | mips64vrel-*-elf*) mips64orion-*-elf* | mips64orionel-*-elf*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elforion.h mips/elf.h" tmake_file="mips/t-elf" - tm_defines="${tm_defines} MIPS_ISA_DEFAULT=3 MIPS_ABI_DEFAULT=ABI_O64" + tm_defines="${tm_defines} MIPS_ISA_DEFAULT=MIPS_ISA_MIPS3 MIPS_ABI_DEFAULT=ABI_O64" ;; mips*-*-rtems*) tm_file="elfos.h newlib-stdint.h ${tm_file} mips/elf.h mips/rtems.h rtems.h" @@ -5367,16 +5367,16 @@ case ${target} in default_mips_abi=$with_abi fi case ${default_mips_arch} in - mips1) tm_defines="$tm_defines MIPS_ISA_DEFAULT=1" ;; - mips2) tm_defines="$tm_defines MIPS_ISA_DEFAULT=2" ;; - mips3) tm_defines="$tm_defines MIPS_ISA_DEFAULT=3" ;; - mips4) tm_defines="$tm_defines MIPS_ISA_DEFAULT=4" ;; - mips32) tm_defines="$tm_defines MIPS_ISA_DEFAULT=32" ;; - mips32r2) tm_defines="$tm_defines MIPS_ISA_DEFAULT=33" ;; - mips32r6) tm_defines="$tm_defines MIPS_ISA_DEFAULT=37" ;; - mips64) tm_defines="$tm_defines MIPS_ISA_DEFAULT=64" ;; - mips64r2) tm_defines="$tm_defines MIPS_ISA_DEFAULT=65" ;; - mips64r6) tm_defines="$tm_defines MIPS_ISA_DEFAULT=69" ;; + mips1) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS1" ;; + mips2) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS2" ;; + mips3) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS3" ;; + mips4) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS4" ;; + mips32) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32" ;; + mips32r2) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R2" ;; + mips32r6) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS32R6" ;; + mips64) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64" ;; + mips64r2) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R2" ;; + mips64r6) tm_defines="$tm_defines MIPS_ISA_DEFAULT=MIPS_ISA_MIPS64R6" ;; esac case ${default_mips_abi} in 32) tm_defines="$tm_defines MIPS_ABI_DEFAULT=ABI_32" ;; diff --git a/gcc/config/mips/mips-cpus.def b/gcc/config/mips/mips-cpus.def index b02294be4b9..45fb6bc8bfd 100644 --- a/gcc/config/mips/mips-cpus.def +++ b/gcc/config/mips/mips-cpus.def @@ -33,146 +33,146 @@ along with GCC; see the file COPYING3. If not see where the arguments are the fields of struct mips_cpu_info. */ /* Entries for generic ISAs. */ -MIPS_CPU ("mips1", PROCESSOR_R3000, 1, 0) -MIPS_CPU ("mips2", PROCESSOR_R6000, 2, PTF_AVOID_BRANCHLIKELY_SIZE) -MIPS_CPU ("mips3", PROCESSOR_R4000, 3, PTF_AVOID_BRANCHLIKELY_SIZE) -MIPS_CPU ("mips4", PROCESSOR_R10000, 4, PTF_AVOID_BRANCHLIKELY_SIZE) +MIPS_CPU ("mips1", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0) +MIPS_CPU ("mips2", PROCESSOR_R6000, MIPS_ISA_MIPS2, PTF_AVOID_BRANCHLIKELY_SIZE) +MIPS_CPU ("mips3", PROCESSOR_R4000, MIPS_ISA_MIPS3, PTF_AVOID_BRANCHLIKELY_SIZE) +MIPS_CPU ("mips4", PROCESSOR_R10000, MIPS_ISA_MIPS4, PTF_AVOID_BRANCHLIKELY_SIZE) /* Prefer not to use branch-likely instructions for generic MIPS32rX and MIPS64rX code. The instructions were officially deprecated in revisions 2 and earlier, but revision 3 is likely to downgrade that to a recommendation to avoid the instructions in code that isn't tuned to a specific processor. */ -MIPS_CPU ("mips32", PROCESSOR_4KC, 32, PTF_AVOID_BRANCHLIKELY_ALWAYS) -MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, 33, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips32", PROCESSOR_4KC, MIPS_ISA_MIPS32, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips32r2", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2, PTF_AVOID_BRANCHLIKELY_ALWAYS) /* mips32r3 is micromips hense why it uses the M4K processor. */ -MIPS_CPU ("mips32r3", PROCESSOR_M4K, 34, PTF_AVOID_BRANCHLIKELY_ALWAYS) -MIPS_CPU ("mips32r5", PROCESSOR_P5600, 36, PTF_AVOID_BRANCHLIKELY_ALWAYS) -MIPS_CPU ("mips32r6", PROCESSOR_I6400, 37, 0) -MIPS_CPU ("mips64", PROCESSOR_5KC, 64, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips32r3", PROCESSOR_M4K, MIPS_ISA_MIPS32R3, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips32r5", PROCESSOR_P5600, MIPS_ISA_MIPS32R5, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips32r6", PROCESSOR_I6400, MIPS_ISA_MIPS32R6, 0) +MIPS_CPU ("mips64", PROCESSOR_5KC, MIPS_ISA_MIPS64, PTF_AVOID_BRANCHLIKELY_ALWAYS) /* ??? For now just tune the generic MIPS64r2 and above for 5KC as well. */ -MIPS_CPU ("mips64r2", PROCESSOR_5KC, 65, PTF_AVOID_BRANCHLIKELY_ALWAYS) -MIPS_CPU ("mips64r3", PROCESSOR_5KC, 66, PTF_AVOID_BRANCHLIKELY_ALWAYS) -MIPS_CPU ("mips64r5", PROCESSOR_5KC, 68, PTF_AVOID_BRANCHLIKELY_ALWAYS) -MIPS_CPU ("mips64r6", PROCESSOR_I6400, 69, 0) +MIPS_CPU ("mips64r2", PROCESSOR_5KC, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips64r3", PROCESSOR_5KC, MIPS_ISA_MIPS64R3, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips64r5", PROCESSOR_5KC, MIPS_ISA_MIPS64R5, PTF_AVOID_BRANCHLIKELY_ALWAYS) +MIPS_CPU ("mips64r6", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0) /* MIPS I processors. */ -MIPS_CPU ("r3000", PROCESSOR_R3000, 1, 0) -MIPS_CPU ("r2000", PROCESSOR_R3000, 1, 0) -MIPS_CPU ("r3900", PROCESSOR_R3900, 1, 0) +MIPS_CPU ("r3000", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0) +MIPS_CPU ("r2000", PROCESSOR_R3000, MIPS_ISA_MIPS1, 0) +MIPS_CPU ("r3900", PROCESSOR_R3900, MIPS_ISA_MIPS1, 0) /* MIPS II processors. */ -MIPS_CPU ("r6000", PROCESSOR_R6000, 2, 0) +MIPS_CPU ("r6000", PROCESSOR_R6000, MIPS_ISA_MIPS2, 0) /* MIPS III processors. */ -MIPS_CPU ("r4000", PROCESSOR_R4000, 3, 0) -MIPS_CPU ("vr4100", PROCESSOR_R4100, 3, 0) -MIPS_CPU ("vr4111", PROCESSOR_R4111, 3, 0) -MIPS_CPU ("vr4120", PROCESSOR_R4120, 3, 0) -MIPS_CPU ("vr4130", PROCESSOR_R4130, 3, 0) -MIPS_CPU ("vr4300", PROCESSOR_R4300, 3, 0) -MIPS_CPU ("r4400", PROCESSOR_R4000, 3, 0) -MIPS_CPU ("r4600", PROCESSOR_R4600, 3, 0) -MIPS_CPU ("orion", PROCESSOR_R4600, 3, 0) -MIPS_CPU ("r4650", PROCESSOR_R4650, 3, 0) -MIPS_CPU ("r4700", PROCESSOR_R4700, 3, 0) -MIPS_CPU ("r5900", PROCESSOR_R5900, 3, 0) +MIPS_CPU ("r4000", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("vr4100", PROCESSOR_R4100, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("vr4111", PROCESSOR_R4111, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("vr4120", PROCESSOR_R4120, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("vr4130", PROCESSOR_R4130, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("vr4300", PROCESSOR_R4300, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("r4400", PROCESSOR_R4000, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("r4600", PROCESSOR_R4600, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("orion", PROCESSOR_R4600, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("r4650", PROCESSOR_R4650, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("r4700", PROCESSOR_R4700, MIPS_ISA_MIPS3, 0) +MIPS_CPU ("r5900", PROCESSOR_R5900, MIPS_ISA_MIPS3, 0) /* ST Loongson 2E/2F processors. */ -MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, 3, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, 3, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("loongson2e", PROCESSOR_LOONGSON_2E, MIPS_ISA_MIPS3, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("loongson2f", PROCESSOR_LOONGSON_2F, MIPS_ISA_MIPS3, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS IV processors. */ -MIPS_CPU ("r8000", PROCESSOR_R8000, 4, 0) -MIPS_CPU ("r10000", PROCESSOR_R10000, 4, 0) -MIPS_CPU ("r12000", PROCESSOR_R10000, 4, 0) -MIPS_CPU ("r14000", PROCESSOR_R10000, 4, 0) -MIPS_CPU ("r16000", PROCESSOR_R10000, 4, 0) -MIPS_CPU ("vr5000", PROCESSOR_R5000, 4, 0) -MIPS_CPU ("vr5400", PROCESSOR_R5400, 4, 0) -MIPS_CPU ("vr5500", PROCESSOR_R5500, 4, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("rm7000", PROCESSOR_R7000, 4, 0) -MIPS_CPU ("rm9000", PROCESSOR_R9000, 4, 0) +MIPS_CPU ("r8000", PROCESSOR_R8000, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("r10000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("r12000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("r14000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("r16000", PROCESSOR_R10000, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("vr5000", PROCESSOR_R5000, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("vr5400", PROCESSOR_R5400, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("vr5500", PROCESSOR_R5500, MIPS_ISA_MIPS4, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("rm7000", PROCESSOR_R7000, MIPS_ISA_MIPS4, 0) +MIPS_CPU ("rm9000", PROCESSOR_R9000, MIPS_ISA_MIPS4, 0) /* MIPS32 processors. */ -MIPS_CPU ("4kc", PROCESSOR_4KC, 32, 0) -MIPS_CPU ("4km", PROCESSOR_4KC, 32, 0) -MIPS_CPU ("4kp", PROCESSOR_4KP, 32, 0) -MIPS_CPU ("4ksc", PROCESSOR_4KC, 32, 0) +MIPS_CPU ("4kc", PROCESSOR_4KC, MIPS_ISA_MIPS32, 0) +MIPS_CPU ("4km", PROCESSOR_4KC, MIPS_ISA_MIPS32, 0) +MIPS_CPU ("4kp", PROCESSOR_4KP, MIPS_ISA_MIPS32, 0) +MIPS_CPU ("4ksc", PROCESSOR_4KC, MIPS_ISA_MIPS32, 0) /* MIPS32 Release 2 processors. */ -MIPS_CPU ("m4k", PROCESSOR_M4K, 33, 0) -MIPS_CPU ("m14kc", PROCESSOR_M4K, 33, 0) -MIPS_CPU ("m14k", PROCESSOR_M4K, 33, 0) -MIPS_CPU ("m14ke", PROCESSOR_M4K, 33, 0) -MIPS_CPU ("m14kec", PROCESSOR_M4K, 33, 0) -MIPS_CPU ("4kec", PROCESSOR_4KC, 33, 0) -MIPS_CPU ("4kem", PROCESSOR_4KC, 33, 0) -MIPS_CPU ("4kep", PROCESSOR_4KP, 33, 0) -MIPS_CPU ("4ksd", PROCESSOR_4KC, 33, 0) - -MIPS_CPU ("24kc", PROCESSOR_24KC, 33, 0) -MIPS_CPU ("24kf2_1", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("24kf", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("24kf1_1", PROCESSOR_24KF1_1, 33, 0) -MIPS_CPU ("24kfx", PROCESSOR_24KF1_1, 33, 0) -MIPS_CPU ("24kx", PROCESSOR_24KF1_1, 33, 0) - -MIPS_CPU ("24kec", PROCESSOR_24KC, 33, 0) /* 24K with DSP. */ -MIPS_CPU ("24kef2_1", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("24kef", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("24kef1_1", PROCESSOR_24KF1_1, 33, 0) -MIPS_CPU ("24kefx", PROCESSOR_24KF1_1, 33, 0) -MIPS_CPU ("24kex", PROCESSOR_24KF1_1, 33, 0) - -MIPS_CPU ("34kc", PROCESSOR_24KC, 33, 0) /* 34K with MT/DSP. */ -MIPS_CPU ("34kf2_1", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("34kf", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("34kf1_1", PROCESSOR_24KF1_1, 33, 0) -MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, 33, 0) -MIPS_CPU ("34kx", PROCESSOR_24KF1_1, 33, 0) -MIPS_CPU ("34kn", PROCESSOR_24KC, 33, 0) /* 34K with MT but no DSP. */ - -MIPS_CPU ("74kc", PROCESSOR_74KC, 33, PTF_AVOID_IMADD) /* 74K with DSPr2. */ -MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) -MIPS_CPU ("74kf", PROCESSOR_74KF2_1, 33, PTF_AVOID_IMADD) -MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) -MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) -MIPS_CPU ("74kx", PROCESSOR_74KF1_1, 33, PTF_AVOID_IMADD) -MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, 33, PTF_AVOID_IMADD) - -MIPS_CPU ("1004kc", PROCESSOR_24KC, 33, 0) /* 1004K with MT/DSP. */ -MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, 33, 0) -MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, 33, 0) - -MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, 33, 0) +MIPS_CPU ("m4k", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("m14kc", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("m14k", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("m14ke", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("m14kec", PROCESSOR_M4K, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("4kec", PROCESSOR_4KC, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("4kem", PROCESSOR_4KC, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("4kep", PROCESSOR_4KP, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("4ksd", PROCESSOR_4KC, MIPS_ISA_MIPS32R2, 0) + +MIPS_CPU ("24kc", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kf2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kf", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kf1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kfx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) + +MIPS_CPU ("24kec", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) /* 24K with DSP. */ +MIPS_CPU ("24kef2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kef", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kef1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kefx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("24kex", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) + +MIPS_CPU ("34kc", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) /* 34K with MT/DSP. */ +MIPS_CPU ("34kf2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("34kf", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("34kf1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("34kfx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("34kx", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("34kn", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) /* 34K with MT but no DSP. */ + +MIPS_CPU ("74kc", PROCESSOR_74KC, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD) /* 74K with DSPr2. */ +MIPS_CPU ("74kf2_1", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD) +MIPS_CPU ("74kf", PROCESSOR_74KF2_1, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD) +MIPS_CPU ("74kf1_1", PROCESSOR_74KF1_1, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD) +MIPS_CPU ("74kfx", PROCESSOR_74KF1_1, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD) +MIPS_CPU ("74kx", PROCESSOR_74KF1_1, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD) +MIPS_CPU ("74kf3_2", PROCESSOR_74KF3_2, MIPS_ISA_MIPS32R2, PTF_AVOID_IMADD) + +MIPS_CPU ("1004kc", PROCESSOR_24KC, MIPS_ISA_MIPS32R2, 0) /* 1004K with MT/DSP. */ +MIPS_CPU ("1004kf2_1", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("1004kf", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) +MIPS_CPU ("1004kf1_1", PROCESSOR_24KF1_1, MIPS_ISA_MIPS32R2, 0) + +MIPS_CPU ("interaptiv", PROCESSOR_24KF2_1, MIPS_ISA_MIPS32R2, 0) /* MIPS32 Release 5 processors. */ -MIPS_CPU ("p5600", PROCESSOR_P5600, 36, (PTF_AVOID_BRANCHLIKELY_SPEED +MIPS_CPU ("p5600", PROCESSOR_P5600, MIPS_ISA_MIPS32R5, (PTF_AVOID_BRANCHLIKELY_SPEED | PTF_AVOID_IMADD)) -MIPS_CPU ("m5100", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("m5101", PROCESSOR_M5100, 36, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("m5100", PROCESSOR_M5100, MIPS_ISA_MIPS32R5, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("m5101", PROCESSOR_M5100, MIPS_ISA_MIPS32R5, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 processors. */ -MIPS_CPU ("5kc", PROCESSOR_5KC, 64, 0) -MIPS_CPU ("5kf", PROCESSOR_5KF, 64, 0) -MIPS_CPU ("20kc", PROCESSOR_20KC, 64, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("sb1", PROCESSOR_SB1, 64, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("sb1a", PROCESSOR_SB1A, 64, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("sr71000", PROCESSOR_SR71000, 64, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("xlr", PROCESSOR_XLR, 64, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("5kc", PROCESSOR_5KC, MIPS_ISA_MIPS64, 0) +MIPS_CPU ("5kf", PROCESSOR_5KF, MIPS_ISA_MIPS64, 0) +MIPS_CPU ("20kc", PROCESSOR_20KC, MIPS_ISA_MIPS64, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("sb1", PROCESSOR_SB1, MIPS_ISA_MIPS64, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("sb1a", PROCESSOR_SB1A, MIPS_ISA_MIPS64, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("sr71000", PROCESSOR_SR71000, MIPS_ISA_MIPS64, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("xlr", PROCESSOR_XLR, MIPS_ISA_MIPS64, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 2 processors. */ -MIPS_CPU ("loongson3a", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("gs464", PROCESSOR_GS464, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("gs464e", PROCESSOR_GS464E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("gs264e", PROCESSOR_GS264E, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("octeon", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("octeon+", PROCESSOR_OCTEON, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, 65, PTF_AVOID_BRANCHLIKELY_SPEED) -MIPS_CPU ("xlp", PROCESSOR_XLP, 65, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("loongson3a", PROCESSOR_GS464, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464", PROCESSOR_GS464, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs464e", PROCESSOR_GS464E, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("gs264e", PROCESSOR_GS264E, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("octeon", PROCESSOR_OCTEON, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("octeon+", PROCESSOR_OCTEON, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("octeon2", PROCESSOR_OCTEON2, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("octeon3", PROCESSOR_OCTEON3, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) +MIPS_CPU ("xlp", PROCESSOR_XLP, MIPS_ISA_MIPS64R2, PTF_AVOID_BRANCHLIKELY_SPEED) /* MIPS64 Release 6 processors. */ -MIPS_CPU ("i6400", PROCESSOR_I6400, 69, 0) -MIPS_CPU ("i6500", PROCESSOR_I6400, 69, 0) -MIPS_CPU ("p6600", PROCESSOR_P6600, 69, 0) +MIPS_CPU ("i6400", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0) +MIPS_CPU ("i6500", PROCESSOR_I6400, MIPS_ISA_MIPS64R6, 0) +MIPS_CPU ("p6600", PROCESSOR_P6600, MIPS_ISA_MIPS64R6, 0) diff --git a/gcc/config/mips/mips.c b/gcc/config/mips/mips.c index 2f7ffe846d8..493d3de487b 100644 --- a/gcc/config/mips/mips.c +++ b/gcc/config/mips/mips.c @@ -19817,9 +19817,12 @@ mips_set_architecture (const struct mips_cpu_info *info) mips_arch_info = info; mips_arch = info->cpu; mips_isa = info->isa; - if (mips_isa < 32) + if (mips_isa < MIPS_ISA_MIPS32) mips_isa_rev = 0; else + /* we can do this is due to the + * enum of MIPS32rN is from 32 to 37 + * enum of MIPS64rN is from 64 to 69 */ mips_isa_rev = (mips_isa & 31) + 1; } } diff --git a/gcc/config/mips/mips.h b/gcc/config/mips/mips.h index 47aac9d3d61..973372e787f 100644 --- a/gcc/config/mips/mips.h +++ b/gcc/config/mips/mips.h @@ -42,6 +42,23 @@ extern int target_flags_explicit; #define ABI_EABI 3 #define ABI_O64 4 +enum mips_isa { + MIPS_ISA_MIPS1 = 1, + MIPS_ISA_MIPS2 = 2, + MIPS_ISA_MIPS3 = 3, + MIPS_ISA_MIPS4 = 4, + MIPS_ISA_MIPS32 = 32, + MIPS_ISA_MIPS32R2 = 33, + MIPS_ISA_MIPS32R3 = 34, + MIPS_ISA_MIPS32R5 = 36, + MIPS_ISA_MIPS32R6 = 37, + MIPS_ISA_MIPS64 = 64, + MIPS_ISA_MIPS64R2 = 65, + MIPS_ISA_MIPS64R3 = 66, + MIPS_ISA_MIPS64R5 = 68, + MIPS_ISA_MIPS64R6 = 69 +}; + /* Masks that affect tuning. PTF_AVOID_BRANCHLIKELY_SPEED @@ -81,7 +98,7 @@ struct mips_cpu_info { enum processor cpu; /* The ISA level that the processor implements. */ - int isa; + enum mips_isa isa; /* A mask of PTF_* values. */ unsigned int tune_flags; @@ -232,7 +249,7 @@ struct mips_cpu_info { /* Generate mips16 code */ #define TARGET_MIPS16 ((target_flags & MASK_MIPS16) != 0) /* Generate mips16e code. Default 16bit ASE for mips32* and mips64* */ -#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= 32) +#define GENERATE_MIPS16E (TARGET_MIPS16 && mips_isa >= MIPS_ISA_MIPS32) /* Generate mips16e register save/restore sequences. */ #define GENERATE_MIPS16E_SAVE_RESTORE (GENERATE_MIPS16E && mips_abi == ABI_32) @@ -247,20 +264,20 @@ struct mips_cpu_info { (TARGET_MIPS16 && mips_code_readable >= CODE_READABLE_PCREL) /* Generic ISA defines. */ -#define ISA_MIPS1 (mips_isa == 1) -#define ISA_MIPS2 (mips_isa == 2) -#define ISA_MIPS3 (mips_isa == 3) -#define ISA_MIPS4 (mips_isa == 4) -#define ISA_MIPS32 (mips_isa == 32) -#define ISA_MIPS32R2 (mips_isa == 33) -#define ISA_MIPS32R3 (mips_isa == 34) -#define ISA_MIPS32R5 (mips_isa == 36) -#define ISA_MIPS32R6 (mips_isa == 37) -#define ISA_MIPS64 (mips_isa == 64) -#define ISA_MIPS64R2 (mips_isa == 65) -#define ISA_MIPS64R3 (mips_isa == 66) -#define ISA_MIPS64R5 (mips_isa == 68) -#define ISA_MIPS64R6 (mips_isa == 69) +#define ISA_MIPS1 (mips_isa == MIPS_ISA_MIPS1) +#define ISA_MIPS2 (mips_isa == MIPS_ISA_MIPS2) +#define ISA_MIPS3 (mips_isa == MIPS_ISA_MIPS3) +#define ISA_MIPS4 (mips_isa == MIPS_ISA_MIPS4) +#define ISA_MIPS32 (mips_isa == MIPS_ISA_MIPS32) +#define ISA_MIPS32R2 (mips_isa == MIPS_ISA_MIPS32R2) +#define ISA_MIPS32R3 (mips_isa == MIPS_ISA_MIPS32R3) +#define ISA_MIPS32R5 (mips_isa == MIPS_ISA_MIPS32R5) +#define ISA_MIPS32R6 (mips_isa == MIPS_ISA_MIPS32R6) +#define ISA_MIPS64 (mips_isa == MIPS_ISA_MIPS64) +#define ISA_MIPS64R2 (mips_isa == MIPS_ISA_MIPS64R2) +#define ISA_MIPS64R3 (mips_isa == MIPS_ISA_MIPS64R3) +#define ISA_MIPS64R5 (mips_isa == MIPS_ISA_MIPS64R5) +#define ISA_MIPS64R6 (mips_isa == MIPS_ISA_MIPS64R6) /* Architecture target defines. */ #define TARGET_LOONGSON_2E (mips_arch == PROCESSOR_LOONGSON_2E) @@ -511,12 +528,13 @@ struct mips_cpu_info { builtin_define ("__mips=4"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS4"); \ } \ - else if (mips_isa >= 32 && mips_isa < 64) \ + else if (mips_isa >= MIPS_ISA_MIPS32 \ + && mips_isa < MIPS_ISA_MIPS64) \ { \ builtin_define ("__mips=32"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS32"); \ } \ - else if (mips_isa >= 64) \ + else if (mips_isa >= MIPS_ISA_MIPS64) \ { \ builtin_define ("__mips=64"); \ builtin_define ("_MIPS_ISA=_MIPS_ISA_MIPS64"); \ @@ -708,25 +726,25 @@ struct mips_cpu_info { #endif #ifndef MULTILIB_ISA_DEFAULT -#if MIPS_ISA_DEFAULT == 1 +#if MIPS_ISA_DEFAULT == MIPS_ISA_MIPS1 #define MULTILIB_ISA_DEFAULT "mips1" -#elif MIPS_ISA_DEFAULT == 2 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS2 #define MULTILIB_ISA_DEFAULT "mips2" -#elif MIPS_ISA_DEFAULT == 3 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS3 #define MULTILIB_ISA_DEFAULT "mips3" -#elif MIPS_ISA_DEFAULT == 4 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS4 #define MULTILIB_ISA_DEFAULT "mips4" -#elif MIPS_ISA_DEFAULT == 32 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32 #define MULTILIB_ISA_DEFAULT "mips32" -#elif MIPS_ISA_DEFAULT == 33 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R2 #define MULTILIB_ISA_DEFAULT "mips32r2" -#elif MIPS_ISA_DEFAULT == 37 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS32R6 #define MULTILIB_ISA_DEFAULT "mips32r6" -#elif MIPS_ISA_DEFAULT == 64 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64 #define MULTILIB_ISA_DEFAULT "mips64" -#elif MIPS_ISA_DEFAULT == 65 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R2 #define MULTILIB_ISA_DEFAULT "mips64r2" -#elif MIPS_ISA_DEFAULT == 69 +#elif MIPS_ISA_DEFAULT == MIPS_ISA_MIPS64R6 #define MULTILIB_ISA_DEFAULT "mips64r6" #else #define MULTILIB_ISA_DEFAULT "mips1" @@ -1275,12 +1293,12 @@ struct mips_cpu_info { && !TARGET_MICROMIPS) /* Likewise mtc1 and mfc1. */ -#define ISA_HAS_XFER_DELAY (mips_isa <= 3 \ +#define ISA_HAS_XFER_DELAY (mips_isa <= MIPS_ISA_MIPS3 \ && !TARGET_MIPS5900 \ && !TARGET_LOONGSON_2EF) /* Likewise floating-point comparisons. */ -#define ISA_HAS_FCMP_DELAY (mips_isa <= 3 \ +#define ISA_HAS_FCMP_DELAY (mips_isa <= MIPS_ISA_MIPS3 \ && !TARGET_MIPS5900 \ && !TARGET_LOONGSON_2EF) @@ -1305,7 +1323,7 @@ struct mips_cpu_info { #define ISA_HAS_SYNCI (mips_isa_rev >= 2 && !TARGET_MIPS16) /* ISA includes sync. */ -#define ISA_HAS_SYNC ((mips_isa >= 2 || TARGET_MIPS3900) && !TARGET_MIPS16) +#define ISA_HAS_SYNC ((mips_isa >= MIPS_ISA_MIPS2 || TARGET_MIPS3900) && !TARGET_MIPS16) #define GENERATE_SYNC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ @@ -1314,7 +1332,7 @@ struct mips_cpu_info { /* ISA includes ll and sc. Note that this implies ISA_HAS_SYNC because the expanders use both ISA_HAS_SYNC and ISA_HAS_LL_SC instructions. */ -#define ISA_HAS_LL_SC (mips_isa >= 2 && !TARGET_MIPS5900 && !TARGET_MIPS16) +#define ISA_HAS_LL_SC (mips_isa >= MIPS_ISA_MIPS2 && !TARGET_MIPS5900 && !TARGET_MIPS16) #define GENERATE_LL_SC \ (target_flags_explicit & MASK_LLSC \ ? TARGET_LLSC && !TARGET_MIPS16 \ @@ -1342,7 +1360,7 @@ struct mips_cpu_info { #define ISA_HAS_POP (TARGET_OCTEON && !TARGET_MIPS16) /* The CACHE instruction is available in non-MIPS16 code. */ -#define TARGET_CACHE_BUILTIN (mips_isa >= 3) +#define TARGET_CACHE_BUILTIN (mips_isa >= MIPS_ISA_MIPS3) /* The CACHE instruction is available. */ #define ISA_HAS_CACHE (TARGET_CACHE_BUILTIN && !TARGET_MIPS16) diff --git a/gcc/config/mips/netbsd.h b/gcc/config/mips/netbsd.h index 5844f006a5d..85c27793d4e 100644 --- a/gcc/config/mips/netbsd.h +++ b/gcc/config/mips/netbsd.h @@ -84,9 +84,10 @@ along with GCC; see the file COPYING3. If not see builtin_define ("__mips=3"); \ else if (ISA_MIPS4) \ builtin_define ("__mips=4"); \ - else if (mips_isa >= 32 && mips_isa < 64) \ + else if (mips_isa >= MIPS_ISA_MIPS32 \ + && mips_isa < MIPS_ISA_MIPS64) \ builtin_define ("__mips=32"); \ - else if (mips_isa >= 64) \ + else if (mips_isa >= MIPS_ISA_64) \ builtin_define ("__mips=64"); \ if (mips_isa_rev > 0) \ builtin_define_with_int_value ("__mips_isa_rev", \