From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1035) id 23FF13857800; Mon, 13 Sep 2021 10:27:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 23FF13857800 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Richard Earnshaw To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-3481] arm: expand handling of movmisalign for DImode [PR102125] X-Act-Checkin: gcc X-Git-Author: Richard Earnshaw X-Git-Refname: refs/heads/master X-Git-Oldrev: 408e8b906632f215f6652b8851bba612cde07c25 X-Git-Newrev: f0cfd070b68772eaaa19a3b711fbd9e85b244240 Message-Id: <20210913102717.23FF13857800@sourceware.org> Date: Mon, 13 Sep 2021 10:27:17 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 13 Sep 2021 10:27:17 -0000 https://gcc.gnu.org/g:f0cfd070b68772eaaa19a3b711fbd9e85b244240 commit r12-3481-gf0cfd070b68772eaaa19a3b711fbd9e85b244240 Author: Richard Earnshaw Date: Fri Sep 3 16:53:13 2021 +0100 arm: expand handling of movmisalign for DImode [PR102125] DImode is currently handled only for machines with vector modes enabled, but this is unduly restrictive and is generally better done in core registers. gcc/ChangeLog: PR target/102125 * config/arm/arm.md (movmisaligndi): New define_expand. * config/arm/vec-common.md (movmisalign): Iterate over VDQ mode. Diff: --- gcc/config/arm/arm.md | 16 ++++++++++++++++ gcc/config/arm/vec-common.md | 4 ++-- 2 files changed, 18 insertions(+), 2 deletions(-) diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 5d3f21b91c4..4adc976b8b6 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -12617,6 +12617,22 @@ }" ) +;; movmisalign for DImode +(define_expand "movmisaligndi" + [(match_operand:DI 0 "general_operand") + (match_operand:DI 1 "general_operand")] + "unaligned_access" +{ + rtx lo_op0 = gen_lowpart (SImode, operands[0]); + rtx lo_op1 = gen_lowpart (SImode, operands[1]); + rtx hi_op0 = gen_highpart_mode (SImode, DImode, operands[0]); + rtx hi_op1 = gen_highpart_mode (SImode, DImode, operands[1]); + + emit_insn (gen_movmisalignsi (lo_op0, lo_op1)); + emit_insn (gen_movmisalignsi (hi_op0, hi_op1)); + DONE; +}) + ;; movmisalign patterns for HImode and SImode. (define_expand "movmisalign" [(match_operand:HSI 0 "general_operand") diff --git a/gcc/config/arm/vec-common.md b/gcc/config/arm/vec-common.md index 68de4f0f943..e71d9b3811f 100644 --- a/gcc/config/arm/vec-common.md +++ b/gcc/config/arm/vec-common.md @@ -281,8 +281,8 @@ }) (define_expand "movmisalign" - [(set (match_operand:VDQX 0 "neon_perm_struct_or_reg_operand") - (unspec:VDQX [(match_operand:VDQX 1 "neon_perm_struct_or_reg_operand")] + [(set (match_operand:VDQ 0 "neon_perm_struct_or_reg_operand") + (unspec:VDQ [(match_operand:VDQ 1 "neon_perm_struct_or_reg_operand")] UNSPEC_MISALIGNED_ACCESS))] "ARM_HAVE__LDST && !BYTES_BIG_ENDIAN && unaligned_access && !TARGET_REALLY_IWMMXT"