From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2078) id 7C30B3858031; Tue, 14 Sep 2021 04:35:38 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 7C30B3858031 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: hongtao Liu To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-3506] AVX512FP16: Add testcase for vrcpph/vrcpsh/vscalefph/vscalefsh. X-Act-Checkin: gcc X-Git-Author: liuhongt X-Git-Refname: refs/heads/master X-Git-Oldrev: bf4c12404fbbc6b21ab4ca2e5e8c6b6b1afe4190 X-Git-Newrev: 03f0cbccb6dc0df8b9026a7f7ec06acdb98531d1 Message-Id: <20210914043538.7C30B3858031@sourceware.org> Date: Tue, 14 Sep 2021 04:35:38 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Sep 2021 04:35:38 -0000 https://gcc.gnu.org/g:03f0cbccb6dc0df8b9026a7f7ec06acdb98531d1 commit r12-3506-g03f0cbccb6dc0df8b9026a7f7ec06acdb98531d1 Author: liuhongt Date: Mon Mar 2 17:02:57 2020 +0800 AVX512FP16: Add testcase for vrcpph/vrcpsh/vscalefph/vscalefsh. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-vrcpph-1a.c: New test. * gcc.target/i386/avx512fp16-vrcpph-1b.c: Ditto. * gcc.target/i386/avx512fp16-vrcpsh-1a.c: Ditto. * gcc.target/i386/avx512fp16-vrcpsh-1b.c: Ditto. * gcc.target/i386/avx512fp16-vscalefph-1a.c: Ditto. * gcc.target/i386/avx512fp16-vscalefph-1b.c: Ditto. * gcc.target/i386/avx512fp16-vscalefsh-1a.c: Ditto. * gcc.target/i386/avx512fp16-vscalefsh-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vrcpph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vrcpph-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vscalefph-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vscalefph-1b.c: Ditto. Diff: --- .../gcc.target/i386/avx512fp16-vrcpph-1a.c | 19 +++++ .../gcc.target/i386/avx512fp16-vrcpph-1b.c | 79 ++++++++++++++++++ .../gcc.target/i386/avx512fp16-vrcpsh-1a.c | 18 +++++ .../gcc.target/i386/avx512fp16-vrcpsh-1b.c | 57 +++++++++++++ .../gcc.target/i386/avx512fp16-vscalefph-1a.c | 25 ++++++ .../gcc.target/i386/avx512fp16-vscalefph-1b.c | 94 ++++++++++++++++++++++ .../gcc.target/i386/avx512fp16-vscalefsh-1a.c | 23 ++++++ .../gcc.target/i386/avx512fp16-vscalefsh-1b.c | 58 +++++++++++++ .../gcc.target/i386/avx512fp16vl-vrcpph-1a.c | 29 +++++++ .../gcc.target/i386/avx512fp16vl-vrcpph-1b.c | 16 ++++ .../gcc.target/i386/avx512fp16vl-vscalefph-1a.c | 29 +++++++ .../gcc.target/i386/avx512fp16vl-vscalefph-1b.c | 16 ++++ 12 files changed, 463 insertions(+) diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1a.c new file mode 100644 index 00000000000..6a5c642d7d8 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1a.c @@ -0,0 +1,19 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512h res; +volatile __m512h x1; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_rcp_ph (x1); + res = _mm512_mask_rcp_ph (res, m32, x1); + res = _mm512_maskz_rcp_ph (m32, x1); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1b.c new file mode 100644 index 00000000000..4a65451af3b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpph-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(rcp_ph) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = 1. / v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = 1. / v2.f32[i]; + } + + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(rcp_ph) (&exp, src1, NET_MASK, 0); + HF(res) = INTRINSIC (_rcp_ph) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _rcp_ph); + + init_dest(&res, &exp); + EMULATE(rcp_ph) (&exp, src1, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_rcp_ph) (HF(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_rcp_ph); + + EMULATE(rcp_ph) (&exp, src1, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_rcp_ph) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_rcp_ph); + + if (n_errs != 0) + abort (); +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1a.c new file mode 100644 index 00000000000..0a5a18e8b84 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1a.c @@ -0,0 +1,18 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vrcpsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res, x1, x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_rcp_sh (x1, x2); + res = _mm_mask_rcp_sh (res, m8, x1, x2); + res = _mm_maskz_rcp_sh (m8, x1, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1b.c new file mode 100644 index 00000000000..531689569cb --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vrcpsh-1b.c @@ -0,0 +1,57 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_rcp_sh(V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = 1. / v1.f32[0]; + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + + emulate_rcp_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_rcp_sh(exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_rcp_sh"); + + init_dest(&res, &exp); + emulate_rcp_sh(&exp, src1, 0x1, 0); + res.xmmh[0] = _mm_mask_rcp_sh(res.xmmh[0], 0x1, exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_mask_rcp_sh"); + + emulate_rcp_sh(&exp, src1, 0x3, 1); + res.xmmh[0] = _mm_maskz_rcp_sh(0x3, exp.xmmh[0], src1.xmmh[0]); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_rcp_sh"); + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1a.c new file mode 100644 index 00000000000..f3d27898f27 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1a.c @@ -0,0 +1,25 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512h res, res1, res2; +volatile __m512h x1, x2; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_scalef_ph (x1, x2); + res1 = _mm512_mask_scalef_ph (res1, m32, x1, x2); + res2 = _mm512_maskz_scalef_ph (m32, x1, x2); + res = _mm512_scalef_round_ph (x1, x2, 8); + res1 = _mm512_mask_scalef_round_ph (res1, m32, x1, x2, 8); + res2 = _mm512_maskz_scalef_round_ph (m32, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c new file mode 100644 index 00000000000..7c7288d6eb3 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefph-1b.c @@ -0,0 +1,94 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define DEBUG + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(scalef_ph) (V512 * dest, V512 op1, V512 op2, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.f32[i] = 0; + } + else { + v5.u32[i] = v7.u32[i]; + } + } + else { + v5.f32[i] = v1.f32[i] * powf(2.0f, floorf(v3.f32[i])); + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + v6.f32[i] = 0; + } + else { + v6.u32[i] = v8.u32[i]; + } + } + else { + v6.f32[i] = v2.f32[i] * powf(2.0f, floorf(v4.f32[i])); + } + } + *dest = pack_twops_2ph(v5, v6); +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(scalef_ph) (&exp, src1, src2, NET_MASK, 0); + HF(res) = INTRINSIC (_scalef_ph) (HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _scalef_ph); + + init_dest(&res, &exp); + EMULATE(scalef_ph) (&exp, src1, src2, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_scalef_ph) (HF(res), MASK_VALUE, HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_scalef_ph); + + EMULATE(scalef_ph) (&exp, src1, src2, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_scalef_ph) (ZMASK_VALUE, HF(src1), HF(src2)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_scalef_ph); + +#if AVX512F_LEN == 512 + EMULATE(scalef_ph) (&exp, src1, src2, NET_MASK, 0); + HF(res) = INTRINSIC (_scalef_round_ph) (HF(src1), HF(src2), 0x04); + CHECK_RESULT (&res, &exp, N_ELEMS, _scalef_round_ph); + + init_dest(&res, &exp); + EMULATE(scalef_ph) (&exp, src1, src2, MASK_VALUE, 0); + HF(res) = INTRINSIC (_mask_scalef_round_ph) (HF(res), MASK_VALUE, HF(src1), HF(src2), 0x04); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_scalef_round_ph); + + EMULATE(scalef_ph) (&exp, src1, src2, ZMASK_VALUE, 1); + HF(res) = INTRINSIC (_maskz_scalef_round_ph) (ZMASK_VALUE, HF(src1), HF(src2), 0x04); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_scalef_round_ph); +#endif + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1a.c new file mode 100644 index 00000000000..999c04849e9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1a.c @@ -0,0 +1,23 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefsh\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m128h res, x1, x2; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm_scalef_sh (x1, x2); + res = _mm_mask_scalef_sh (res, m8, x1, x2); + res = _mm_maskz_scalef_sh (m8, x1, x2); + res = _mm_scalef_round_sh (x1, x2, 4); + res = _mm_mask_scalef_round_sh (res, m8, x1, x2, 8); + res = _mm_maskz_scalef_round_sh (m8, x1, x2, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1b.c new file mode 100644 index 00000000000..5db7be0715f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vscalefsh-1b.c @@ -0,0 +1,58 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS 8 + +void NOINLINE +emulate_scalef_sh(V512 * dest, V512 op1, V512 op2, + __mmask8 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + + unpack_ph_2twops(op1, &v1, &v2); + unpack_ph_2twops(op2, &v3, &v4); + unpack_ph_2twops(*dest, &v7, &v8); + + if ((k&1) || !k) + v5.f32[0] = v1.f32[0] * powf(2.0f, floorf(v3.f32[0])); + else if (zero_mask) + v5.f32[0] = 0; + else + v5.f32[0] = v7.f32[0]; + + for (i = 1; i < 8; i++) + v5.f32[i] = v1.f32[i]; + + *dest = pack_twops_2ph(v5, v6); +} + +void +test_512 (void) +{ + V512 res; + V512 exp; + + init_src(); + emulate_scalef_sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_scalef_round_sh(src1.xmmh[0], src2.xmmh[0], (0x00 | 0x08)); + check_results(&res, &exp, N_ELEMS, "_mm_scalef_round_sh"); + + init_dest(&res, &exp); + emulate_scalef_sh(&exp, src1, src2, 0x1, 0); + res.xmmh[0] = _mm_mask_scalef_round_sh(res.xmmh[0], 0x1, src1.xmmh[0], src2.xmmh[0], (0x00 | 0x08)); + check_results(&res, &exp, N_ELEMS, "_mm_mask_scalef_round_sh"); + + emulate_scalef_sh(&exp, src1, src2, 0x3, 1); + res.xmmh[0] = _mm_maskz_scalef_round_sh(0x3, src1.xmmh[0], src2.xmmh[0], (0x00 | 0x08)); + check_results(&res, &exp, N_ELEMS, "_mm_maskz_scalef_round_sh"); + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1a.c new file mode 100644 index 00000000000..5894dbc679f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vrcpph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1; +volatile __m128h x2; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_rcp_ph (x1); + res1 = _mm256_mask_rcp_ph (res1, m16, x1); + res1 = _mm256_maskz_rcp_ph (m16, x1); + + res2 = _mm_rcp_ph (x2); + res2 = _mm_mask_rcp_ph (res2, m8, x2); + res2 = _mm_maskz_rcp_ph (m8, x2); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1b.c new file mode 100644 index 00000000000..a6b1e376a8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vrcpph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrcpph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vrcpph-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1a.c new file mode 100644 index 00000000000..22231d628cf --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vscalefph\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256h res1; +volatile __m128h res2; +volatile __m256h x1,x2; +volatile __m128h x3, x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_scalef_ph (x1, x2); + res1 = _mm256_mask_scalef_ph (res1, m16, x1, x2); + res1 = _mm256_maskz_scalef_ph (m16, x1, x2); + + res2 = _mm_scalef_ph (x3, x4); + res2 = _mm_mask_scalef_ph (res2, m8, x3, x4); + res2 = _mm_maskz_scalef_ph (m8, x3, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1b.c new file mode 100644 index 00000000000..5c12d08e2e1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vscalefph-1b.c @@ -0,0 +1,16 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define DEBUG +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vscalefph-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vscalefph-1b.c" +