From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2078) id 5C96F3857C6A; Thu, 16 Sep 2021 05:37:59 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 5C96F3857C6A MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: hongtao Liu To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-3566] AVX512FP16: Add testcase for vcvtph2w/vcvtph2uw/vcvtph2dq/vcvtph2udq/vcvtph2qq/vcvtph2uqq. X-Act-Checkin: gcc X-Git-Author: liuhongt X-Git-Refname: refs/heads/master X-Git-Oldrev: bd610db0d52cd1e4d972ff140c091d42ef486be4 X-Git-Newrev: 038afce92d86f0a291b700b76155090f94489cfd Message-Id: <20210916053759.5C96F3857C6A@sourceware.org> Date: Thu, 16 Sep 2021 05:37:59 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Sep 2021 05:37:59 -0000 https://gcc.gnu.org/g:038afce92d86f0a291b700b76155090f94489cfd commit r12-3566-g038afce92d86f0a291b700b76155090f94489cfd Author: liuhongt Date: Mon Mar 2 17:14:10 2020 +0800 AVX512FP16: Add testcase for vcvtph2w/vcvtph2uw/vcvtph2dq/vcvtph2udq/vcvtph2qq/vcvtph2uqq. gcc/testsuite/ChangeLog: * gcc.target/i386/avx512fp16-helper.h (V512): Add QI components. * gcc.target/i386/avx512fp16-vcvtph2dq-1a.c: New test. * gcc.target/i386/avx512fp16-vcvtph2dq-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2qq-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2qq-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2udq-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2udq-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2uw-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2uw-1b.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2w-1a.c: Ditto. * gcc.target/i386/avx512fp16-vcvtph2w-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c: Ditto. * gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c: Ditto. Diff: --- gcc/testsuite/gcc.target/i386/avx512fp16-helper.h | 25 ++++++- .../gcc.target/i386/avx512fp16-vcvtph2dq-1a.c | 24 +++++++ .../gcc.target/i386/avx512fp16-vcvtph2dq-1b.c | 79 ++++++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtph2qq-1a.c | 24 +++++++ .../gcc.target/i386/avx512fp16-vcvtph2qq-1b.c | 78 ++++++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtph2udq-1a.c | 24 +++++++ .../gcc.target/i386/avx512fp16-vcvtph2udq-1b.c | 79 ++++++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c | 24 +++++++ .../gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c | 78 ++++++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtph2uw-1a.c | 24 +++++++ .../gcc.target/i386/avx512fp16-vcvtph2uw-1b.c | 84 ++++++++++++++++++++++ .../gcc.target/i386/avx512fp16-vcvtph2w-1a.c | 24 +++++++ .../gcc.target/i386/avx512fp16-vcvtph2w-1b.c | 83 +++++++++++++++++++++ .../gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c | 27 +++++++ .../gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c | 15 ++++ .../gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c | 27 +++++++ .../gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c | 15 ++++ .../gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c | 27 +++++++ .../gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c | 15 ++++ .../gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c | 27 +++++++ .../gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c | 15 ++++ .../gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c | 29 ++++++++ .../gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c | 15 ++++ .../gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c | 29 ++++++++ .../gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c | 15 ++++ 25 files changed, 903 insertions(+), 3 deletions(-) diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h index f6f46872c35..aa83b66998c 100644 --- a/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-helper.h @@ -25,13 +25,17 @@ typedef union { __m512 zmm; __m512h zmmh; + __m512i zmmi; __m256 ymm[2]; __m256h ymmh[2]; __m256i ymmi[2]; __m128h xmmh[4]; __m128 xmm[4]; + __m128i xmmi[4]; unsigned short u16[32]; unsigned int u32[16]; + long long s64[8]; + unsigned long long u64[8]; float f32[16]; _Float16 f16[32]; } V512; @@ -162,9 +166,9 @@ init_src() int i; for (i = 0; i < AVX512F_MAX_ELEM; i++) { - v1.f32[i] = -i + 1; + v1.f32[i] = i + 1; v2.f32[i] = i * 0.5f; - v3.f32[i] = i * 2.5f; + v3.f32[i] = i * 1.5f; v4.f32[i] = i - 0.5f; src3.u32[i] = (i + 1) * 10; @@ -217,30 +221,45 @@ init_dest(V512 * res, V512 * exp) #if AVX512F_LEN == 256 #undef HF #undef SF +#undef SI +#undef H_HF #undef NET_MASK -#undef MASK_VALUE +#undef MASK_VALUE +#undef HALF_MASK #undef ZMASK_VALUE #define NET_MASK 0xffff #define MASK_VALUE 0xcccc #define ZMASK_VALUE 0xfcc1 +#define HALF_MASK 0xcc #define HF(x) x.ymmh[0] +#define H_HF(x) x.xmmh[0] #define SF(x) x.ymm[0] +#define SI(x) x.ymmi[0] #elif AVX512F_LEN == 128 #undef HF #undef SF +#undef SI +#undef H_HF #undef NET_MASK #undef MASK_VALUE #undef ZMASK_VALUE +#undef HALF_MASK #define NET_MASK 0xff #define MASK_VALUE 0xcc +#define HALF_MASK MASK_VALUE #define ZMASK_VALUE 0xc1 #define HF(x) x.xmmh[0] #define SF(x) x.xmm[0] +#define SI(x) x.xmmi[0] +#define H_HF(x) x.xmmh[0] #else #define NET_MASK 0xffffffff #define MASK_VALUE 0xcccccccc #define ZMASK_VALUE 0xfcc1fcc1 +#define HALF_MASK 0xcccc #define HF(x) x.zmmh #define SF(x) x.zmm +#define SI(x) x.zmmi +#define H_HF(x) x.ymmh[0] #endif diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1a.c new file mode 100644 index 00000000000..31a56393f0e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i res, res1, res2; +volatile __m256h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epi32 (x1); + res1 = _mm512_mask_cvtph_epi32 (res, m16, x2); + res2 = _mm512_maskz_cvtph_epi32 (m16, x3); + res = _mm512_cvt_roundph_epi32 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epi32 (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epi32 (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1b.c new file mode 100644 index 00000000000..80a85828271 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2dq-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_d) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epi32) (H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epi32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvtph_epi32) (SI(res), HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epi32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epi32) (HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epi32); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epi32) (H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epi32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epi32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epi32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epi32) (HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epi32); +#endif + + if (n_errs != 0) + abort (); +} + + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1a.c new file mode 100644 index 00000000000..d80ee611f3c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i res, res1, res2; +volatile __m128h x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epi64 (x1); + res1 = _mm512_mask_cvtph_epi64 (res, m8, x2); + res2 = _mm512_maskz_cvtph_epi64 (m8, x3); + res = _mm512_cvt_roundph_epi64 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epi64 (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epi64 (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1b.c new file mode 100644 index 00000000000..42b21cf2e4d --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2qq-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_q) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epi64) (src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epi64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvtph_epi64) (SI(res), 0xcc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epi64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfa, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epi64) (0xfa, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epi64); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epi64) (src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epi64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epi64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epi64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfa, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epi64) (0xfa, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epi64); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1a.c new file mode 100644 index 00000000000..b4a833afdab --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i res, res1, res2; +volatile __m256h x1, x2, x3; +volatile __mmask16 m16; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epu32 (x1); + res1 = _mm512_mask_cvtph_epu32 (res, m16, x2); + res2 = _mm512_maskz_cvtph_epu32 (m16, x3); + res = _mm512_cvt_roundph_epu32 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epu32 (res, m16, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epu32 (m16, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1b.c new file mode 100644 index 00000000000..15fa0ba2b4f --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2udq-1b.c @@ -0,0 +1,79 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_d) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u32[i] = 0; + } + else { + v5.u32[i] = dest->u32[i]; + } + } + else { + v5.u32[i] = v1.f32[i]; + + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epu32) (H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epu32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvtph_epu32) (SI(res), HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epu32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epu32) (HALF_MASK, H_HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epu32); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_d)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epu32) (H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epu32); + + init_dest(&res, &exp); + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epu32) (SI(res), HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epu32); + + EMULATE(cvtph2_d)(&exp, src1, HALF_MASK, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epu32) (HALF_MASK, H_HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epu32); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c new file mode 100644 index 00000000000..b4087798be9 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\{rn-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\{rz-sae\}\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i res, res1, res2; +volatile __m128h x1, x2, x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epu64 (x1); + res1 = _mm512_mask_cvtph_epu64 (res, m8, x2); + res2 = _mm512_maskz_cvtph_epu64 (m8, x3); + res = _mm512_cvt_roundph_epu64 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epu64 (res, m8, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epu64 (m8, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c new file mode 100644 index 00000000000..7f34772aca6 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uqq-1b.c @@ -0,0 +1,78 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_q) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 8; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + v5.u64[i] = 0; + } + else { + v5.u64[i] = dest->u64[i]; + } + } + else { + v5.u64[i] = v1.f32[i]; + } + } + *dest = v5; +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epu64) (src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epu64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvtph_epu64) (SI(res), 0xcc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epu64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfc, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epu64) (0xfc, src1.xmmh[0]); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epu64); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_q)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epu64) (src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epu64); + + init_dest(&res, &exp); + EMULATE(cvtph2_q)(&exp, src1, 0xcc, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epu64) (SI(res), 0xcc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epu64); + + EMULATE(cvtph2_q)(&exp, src1, 0xfc, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epu64) (0xfc, src1.xmmh[0], _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epu64); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1a.c new file mode 100644 index 00000000000..262274526b1 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epu16 (x1); + res1 = _mm512_mask_cvtph_epu16 (res, m32, x2); + res2 = _mm512_maskz_cvtph_epu16 (m32, x3); + res = _mm512_cvt_roundph_epu16 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epu16 (res, m32, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epu16 (m32, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1b.c new file mode 100644 index 00000000000..437a1f0eeae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2uw-1b.c @@ -0,0 +1,84 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_w) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + dest->u16[i] = 0; + } + } + else { + dest->u16[i] = v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + dest->u16[i+16] = 0; + } + } + else { + dest->u16[i+16] = v2.f32[i]; + } + } +} + +void +TEST (void) +{ + V512 res; + V512 exp; + + init_src(); + + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epu16) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epu16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvtph_epu16) (SI(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epu16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epu16) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epu16); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epu16) (HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epu16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epu16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epu16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epu16) (ZMASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epu16); +#endif + + if (n_errs != 0) + abort (); +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1a.c new file mode 100644 index 00000000000..bcaa7446d34 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1a.c @@ -0,0 +1,24 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 2 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\{\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\[^\n\r]*%zmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m512i res, res1, res2; +volatile __m512h x1, x2, x3; +volatile __mmask32 m32; + +void extern +avx512f_test (void) +{ + res = _mm512_cvtph_epi16 (x1); + res1 = _mm512_mask_cvtph_epi16 (res, m32, x2); + res2 = _mm512_maskz_cvtph_epi16 (m32, x3); + res = _mm512_cvt_roundph_epi16 (x1, 4); + res1 = _mm512_mask_cvt_roundph_epi16 (res, m32, x2, 8); + res2 = _mm512_maskz_cvt_roundph_epi16 (m32, x3, 11); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1b.c new file mode 100644 index 00000000000..dfa20523932 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vcvtph2w-1b.c @@ -0,0 +1,83 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */ + +#define AVX512FP16 +#include "avx512fp16-helper.h" + +#define N_ELEMS (AVX512F_LEN / 16) + +void NOINLINE +EMULATE(cvtph2_w) (V512 * dest, V512 op1, + __mmask32 k, int zero_mask) +{ + V512 v1, v2, v3, v4, v5, v6, v7, v8; + int i; + __mmask16 m1, m2; + + m1 = k & 0xffff; + m2 = (k >> 16) & 0xffff; + + unpack_ph_2twops(op1, &v1, &v2); + + for (i = 0; i < 16; i++) { + if (((1 << i) & m1) == 0) { + if (zero_mask) { + dest->u16[i] = 0; + } + } + else { + dest->u16[i] = v1.f32[i]; + + } + + if (((1 << i) & m2) == 0) { + if (zero_mask) { + dest->u16[i+16] = 0; + } + } + else { + dest->u16[i+16] = v2.f32[i]; + } + } +} + +void +TEST (void) +{ + V512 res, exp; + + init_src(); + + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvtph_epi16) (HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvtph_epi16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvtph_epi16) (SI(res), MASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvtph_epi16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvtph_epi16) (ZMASK_VALUE, HF(src1)); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvtph_epi16); + +#if AVX512F_LEN == 512 + EMULATE(cvtph2_w)(&exp, src1, NET_MASK, 0); + SI(res) = INTRINSIC (_cvt_roundph_epi16) (HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _cvt_roundph_epi16); + + init_dest(&res, &exp); + EMULATE(cvtph2_w)(&exp, src1, MASK_VALUE, 0); + SI(res) = INTRINSIC (_mask_cvt_roundph_epi16) (SI(res), MASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _mask_cvt_roundph_epi16); + + EMULATE(cvtph2_w)(&exp, src1, ZMASK_VALUE, 1); + SI(res) = INTRINSIC (_maskz_cvt_roundph_epi16) (ZMASK_VALUE, HF(src1), _ROUND_NINT); + CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_cvt_roundph_epi16); +#endif + + if (n_errs != 0) { + abort (); + } +} + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c new file mode 100644 index 00000000000..df653b0b2c7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2dq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epi32 (x3); + res1 = _mm256_mask_cvtph_epi32 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epi32 (m8, x3); + + res2 = _mm_cvtph_epi32 (x3); + res2 = _mm_mask_cvtph_epi32 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epi32 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c new file mode 100644 index 00000000000..93a3e903da4 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2dq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2dq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2dq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c new file mode 100644 index 00000000000..ddc6f2a702e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2qq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epi64 (x3); + res1 = _mm256_mask_cvtph_epi64 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epi64 (m8, x3); + + res2 = _mm_cvtph_epi64 (x3); + res2 = _mm_mask_cvtph_epi64 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epi64 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c new file mode 100644 index 00000000000..5afc5a1836b --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2qq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2qq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2qq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c new file mode 100644 index 00000000000..d07d76647a7 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2udq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epu32 (x3); + res1 = _mm256_mask_cvtph_epu32 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epu32 (m8, x3); + + res2 = _mm_cvtph_epu32 (x3); + res2 = _mm_mask_cvtph_epu32 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epu32 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c new file mode 100644 index 00000000000..d869a0ca259 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2udq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2udq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2udq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c new file mode 100644 index 00000000000..26dbf227d81 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1a.c @@ -0,0 +1,27 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uqq\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i res1; +volatile __m128i res2; +volatile __m128h x3; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epu64 (x3); + res1 = _mm256_mask_cvtph_epu64 (res1, m8, x3); + res1 = _mm256_maskz_cvtph_epu64 (m8, x3); + + res2 = _mm_cvtph_epu64 (x3); + res2 = _mm_mask_cvtph_epu64 (res2, m8, x3); + res2 = _mm_maskz_cvtph_epu64 (m8, x3); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c new file mode 100644 index 00000000000..d9b10a82f8e --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uqq-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uqq-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uqq-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c new file mode 100644 index 00000000000..0f9fd27881c --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2uw\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i res1; +volatile __m128i res2; +volatile __m256h x3; +volatile __m128h x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epu16 (x3); + res1 = _mm256_mask_cvtph_epu16 (res1, m16, x3); + res1 = _mm256_maskz_cvtph_epu16 (m16, x3); + + res2 = _mm_cvtph_epu16 (x4); + res2 = _mm_mask_cvtph_epu16 (res2, m8, x4); + res2 = _mm_maskz_cvtph_epu16 (m8, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c new file mode 100644 index 00000000000..280dcd75320 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2uw-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uw-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2uw-1b.c" + diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c new file mode 100644 index 00000000000..8dee4ee25d0 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1a.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-options "-mavx512fp16 -mavx512vl -O2" } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%ymm\[0-9\]+\[^\n\r]*%ymm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}(?:\n|\[ \\t\]+#)" 1 } } */ +/* { dg-final { scan-assembler-times "vcvtph2w\[ \\t\]+%xmm\[0-9\]+\[^\n\r]*%xmm\[0-9\]+\{%k\[0-9\]\}\{z\}\[^\n\r]*(?:\n|\[ \\t\]+#)" 1 } } */ + +#include + +volatile __m256i res1; +volatile __m128i res2; +volatile __m256h x3; +volatile __m128h x4; +volatile __mmask16 m16; +volatile __mmask8 m8; + +void extern +avx512f_test (void) +{ + res1 = _mm256_cvtph_epi16 (x3); + res1 = _mm256_mask_cvtph_epi16 (res1, m16, x3); + res1 = _mm256_maskz_cvtph_epi16 (m16, x3); + + res2 = _mm_cvtph_epi16 (x4); + res2 = _mm_mask_cvtph_epi16 (res2, m8, x4); + res2 = _mm_maskz_cvtph_epi16 (m8, x4); +} diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c new file mode 100644 index 00000000000..739ba6478ae --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vcvtph2w-1b.c @@ -0,0 +1,15 @@ +/* { dg-do run { target avx512fp16 } } */ +/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */ + +#define AVX512VL +#define AVX512F_LEN 256 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2w-1b.c" + +#undef AVX512F_LEN +#undef AVX512F_LEN_HALF + +#define AVX512F_LEN 128 +#define AVX512F_LEN_HALF 128 +#include "avx512fp16-vcvtph2w-1b.c" +