From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1909) id DF8E83857832; Thu, 16 Sep 2021 11:44:17 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DF8E83857832 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Daniel Hellstrom To: gcc-cvs@gcc.gnu.org Subject: [gcc r11-9003] sparc: Treat more instructions as load or store in errata workarounds X-Act-Checkin: gcc X-Git-Author: Daniel Cederman X-Git-Refname: refs/heads/releases/gcc-11 X-Git-Oldrev: b602b667c05041df22c88fadd91fa8dd92330ce5 X-Git-Newrev: 807c7e12486518a7b23e4e27536a1df28a41774a Message-Id: <20210916114417.DF8E83857832@sourceware.org> Date: Thu, 16 Sep 2021 11:44:17 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Sep 2021 11:44:18 -0000 https://gcc.gnu.org/g:807c7e12486518a7b23e4e27536a1df28a41774a commit r11-9003-g807c7e12486518a7b23e4e27536a1df28a41774a Author: Daniel Cederman Date: Fri Sep 25 13:17:46 2020 +0200 sparc: Treat more instructions as load or store in errata workarounds Check the attribute of instruction to determine if it performs a store or load operation. This more generic approach sees the last instruction in the GOTdata_op model as a potential load and treats the memory barrier as a potential store instruction. gcc/ChangeLog: * config/sparc/sparc.c (store_insn_p): Add predicate for store attributes. (load_insn_p): Add predicate for load attributes. (sparc_do_work_around_errata): Use new predicates. Diff: --- gcc/config/sparc/sparc.c | 49 ++++++++++++++++++++++++++++++++++++++++-------- 1 file changed, 41 insertions(+), 8 deletions(-) diff --git a/gcc/config/sparc/sparc.c b/gcc/config/sparc/sparc.c index fea7d78949d..154ac7e435b 100644 --- a/gcc/config/sparc/sparc.c +++ b/gcc/config/sparc/sparc.c @@ -1053,6 +1053,43 @@ atomic_insn_for_leon3_p (rtx_insn *insn) } } +/* True if INSN is a store instruction. */ + +static bool +store_insn_p (rtx_insn *insn) +{ + if (GET_CODE (PATTERN (insn)) != SET) + return false; + + switch (get_attr_type (insn)) + { + case TYPE_STORE: + case TYPE_FPSTORE: + return true; + default: + return false; + } +} + +/* True if INSN is a load instruction. */ + +static bool +load_insn_p (rtx_insn *insn) +{ + if (GET_CODE (PATTERN (insn)) != SET) + return false; + + switch (get_attr_type (insn)) + { + case TYPE_LOAD: + case TYPE_SLOAD: + case TYPE_FPLOAD: + return true; + default: + return false; + } +} + /* We use a machine specific pass to enable workarounds for errata. We need to have the (essentially) final form of the insn stream in order @@ -1113,9 +1150,7 @@ sparc_do_work_around_errata (void) instruction at branch target. */ if (sparc_fix_ut700 && NONJUMP_INSN_P (insn) - && (set = single_set (insn)) != NULL_RTX - && mem_ref (SET_SRC (set)) - && REG_P (SET_DEST (set))) + && load_insn_p (insn)) { if (jump && jump_to_label_p (jump)) { @@ -1220,7 +1255,7 @@ sparc_do_work_around_errata (void) if (sparc_fix_b2bst && NONJUMP_INSN_P (insn) && (set = single_set (insn)) != NULL_RTX - && MEM_P (SET_DEST (set))) + && store_insn_p (insn)) { /* Sequence B begins with a double-word store. */ bool seq_b = GET_MODE_SIZE (GET_MODE (SET_DEST (set))) == 8; @@ -1253,8 +1288,7 @@ sparc_do_work_around_errata (void) if (seq_b) { /* Add NOP if followed by a store. */ - if ((set = single_set (after)) != NULL_RTX - && MEM_P (SET_DEST (set))) + if (store_insn_p (after)) insert_nop = true; /* Otherwise it is ok. */ @@ -1276,8 +1310,7 @@ sparc_do_work_around_errata (void) /* Add NOP if third instruction is a store. */ if (i == 1 - && (set = single_set (after)) != NULL_RTX - && MEM_P (SET_DEST (set))) + && store_insn_p (after)) insert_nop = true; } }