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* [gcc r12-3648] AVX512FP16: Add testcase for fma instructions
@ 2021-09-18 7:10 hongtao Liu
0 siblings, 0 replies; only message in thread
From: hongtao Liu @ 2021-09-18 7:10 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:630a1249a0053ef61fe50a31a348e78dfb229c22
commit r12-3648-g630a1249a0053ef61fe50a31a348e78dfb229c22
Author: liuhongt <hongtao.liu@intel.com>
Date: Mon Mar 2 17:31:47 2020 +0800
AVX512FP16: Add testcase for fma instructions
gcc/testsuite/ChangeLog:
* gcc.target/i386/avx512fp16-vfmaddXXXph-1a.c: New test.
* gcc.target/i386/avx512fp16-vfmaddXXXph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vfmsubXXXph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vfmsubXXXph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vfnmaddXXXph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vfnmaddXXXph-1b.c: Ditto.
* gcc.target/i386/avx512fp16-vfnmsubXXXph-1a.c: Ditto.
* gcc.target/i386/avx512fp16-vfnmsubXXXph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfmaddXXXph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfmaddXXXph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfmsubXXXph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfmsubXXXph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1b.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1a.c: Ditto.
* gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1b.c: Ditto.
Diff:
---
.../gcc.target/i386/avx512fp16-vfmaddXXXph-1a.c | 28 ++++
.../gcc.target/i386/avx512fp16-vfmaddXXXph-1b.c | 160 +++++++++++++++++++++
.../gcc.target/i386/avx512fp16-vfmsubXXXph-1a.c | 32 +++++
.../gcc.target/i386/avx512fp16-vfmsubXXXph-1b.c | 155 ++++++++++++++++++++
.../gcc.target/i386/avx512fp16-vfnmaddXXXph-1a.c | 28 ++++
.../gcc.target/i386/avx512fp16-vfnmaddXXXph-1b.c | 159 ++++++++++++++++++++
.../gcc.target/i386/avx512fp16-vfnmsubXXXph-1a.c | 32 +++++
.../gcc.target/i386/avx512fp16-vfnmsubXXXph-1b.c | 157 ++++++++++++++++++++
.../gcc.target/i386/avx512fp16vl-vfmaddXXXph-1a.c | 28 ++++
.../gcc.target/i386/avx512fp16vl-vfmaddXXXph-1b.c | 15 ++
.../gcc.target/i386/avx512fp16vl-vfmsubXXXph-1a.c | 28 ++++
.../gcc.target/i386/avx512fp16vl-vfmsubXXXph-1b.c | 15 ++
.../gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1a.c | 28 ++++
.../gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1b.c | 15 ++
.../gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1a.c | 28 ++++
.../gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1b.c | 15 ++
16 files changed, 923 insertions(+)
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddXXXph-1a.c
new file mode 100644
index 00000000000..f9e2777196a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddXXXph-1a.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd231ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd231ph\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512h x1, x2, x3;
+volatile __mmask32 m;
+
+void extern
+avx512f_test (void)
+{
+ x1 = _mm512_fmadd_ph (x1, x2, x3);
+ x1 = _mm512_mask_fmadd_ph (x1, m, x2, x3);
+ x3 = _mm512_mask3_fmadd_ph (x1, x2, x3, m);
+ x1 = _mm512_maskz_fmadd_ph (m, x1, x2, x3);
+ x1 = _mm512_fmadd_round_ph (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+ x1 = _mm512_mask_fmadd_round_ph (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+ x3 = _mm512_mask3_fmadd_round_ph (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+ x1 = _mm512_maskz_fmadd_round_ph (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddXXXph-1b.c
new file mode 100644
index 00000000000..71c2b8fb930
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmaddXXXph-1b.c
@@ -0,0 +1,160 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(fmadd_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = v1.f32[i] * v3.f32[i] + v7.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = v2.f32[i] * v4.f32[i] + v8.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void NOINLINE
+EMULATE(m_fmadd_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = v7.f32[i] * v1.f32[i] + v3.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = v8.f32[i] * v2.f32[i] + v4.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+TEST (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+
+ init_dest(&res, &exp);
+ EMULATE(fmadd_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fmadd_ph) (HF(src1), HF(src2),
+ HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fmadd_ph) (HF(res), MASK_VALUE,
+ HF(src1), HF(src2));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fmadd_ph) (HF(src1), HF(src2),
+ HF(res), MASK_VALUE);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fmadd_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fmadd_ph) (ZMASK_VALUE, HF(src1),
+ HF(src2), HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmadd_ph);
+
+#if AVX512F_LEN == 512
+ init_dest(&res, &exp);
+ EMULATE(fmadd_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fmadd_round_ph) (HF(src1), HF(src2),
+ HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fmadd_round_ph) (HF(res), MASK_VALUE, HF(src1),
+ HF(src2), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmadd_ph);
+
+ EMULATE(fmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fmadd_round_ph) (HF(src1), HF(src2), HF(res),
+ MASK_VALUE, _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fmadd_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fmadd_round_ph) (ZMASK_VALUE, HF(src1), HF(src2),
+ HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmadd_ph);
+#endif
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmsubXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmsubXXXph-1a.c
new file mode 100644
index 00000000000..3b1147a41cd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmsubXXXph-1a.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub231ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub231ph\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512h x1, x2, x3;
+volatile __mmask32 m;
+
+void extern
+avx512f_test (void)
+{
+ x1 = _mm512_fmsub_ph (x1, x2, x3);
+ x1 = _mm512_mask_fmsub_ph (x1, m, x2, x3);
+ x3 = _mm512_mask3_fmsub_ph (x1, x2, x3, m);
+ x1 = _mm512_maskz_fmsub_ph (m, x1, x2, x3);
+ x1 = _mm512_fmsub_round_ph (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT
+ | _MM_FROUND_NO_EXC);
+ x1 = _mm512_mask_fmsub_round_ph (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF
+ | _MM_FROUND_NO_EXC);
+ x3 = _mm512_mask3_fmsub_round_ph (x1, x2, x3, m, _MM_FROUND_TO_POS_INF
+ | _MM_FROUND_NO_EXC);
+ x1 = _mm512_maskz_fmsub_round_ph (m, x1, x2, x3, _MM_FROUND_TO_ZERO
+ | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfmsubXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmsubXXXph-1b.c
new file mode 100644
index 00000000000..abb9a9bc826
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfmsubXXXph-1b.c
@@ -0,0 +1,155 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(fmsub_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = v1.f32[i] * v3.f32[i] - v7.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = v2.f32[i] * v4.f32[i] - v8.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void NOINLINE
+EMULATE(m_fmsub_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = v7.f32[i] * v1.f32[i] - v3.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = v8.f32[i] * v2.f32[i] - v4.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+TEST (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+
+ init_dest(&res, &exp);
+ EMULATE(fmsub_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fmsub_ph) (HF(src1), HF(src2), HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fmsub_ph) (HF(res), MASK_VALUE,
+ HF(src1), HF(src2));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fmsub_ph) (HF(src1), HF(src2), HF(res), MASK_VALUE);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fmsub_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fmsub_ph) (ZMASK_VALUE, HF(src1), HF(src2), HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmsub_ph);
+
+#if AVX512F_LEN == 512
+ init_dest(&res, &exp);
+ EMULATE(fmsub_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fmsub_round_ph) (HF(src1), HF(src2), HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fmsub_round_ph) (HF(res), MASK_VALUE,
+ HF(src1), HF(src2), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fmsub_ph);
+
+ EMULATE(fmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fmsub_round_ph) (HF(src1), HF(src2),
+ HF(res), MASK_VALUE, _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fmsub_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fmsub_round_ph) (ZMASK_VALUE, HF(src1),
+ HF(src2), HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fmsub_ph);
+#endif
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmaddXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmaddXXXph-1a.c
new file mode 100644
index 00000000000..20e77ce7398
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmaddXXXph-1a.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231ph\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512h x1, x2, x3;
+volatile __mmask32 m;
+
+void extern
+avx512f_test (void)
+{
+ x1 = _mm512_fnmadd_ph (x1, x2, x3);
+ x1 = _mm512_mask_fnmadd_ph (x1, m, x2, x3);
+ x3 = _mm512_mask3_fnmadd_ph (x1, x2, x3, m);
+ x1 = _mm512_maskz_fnmadd_ph (m, x1, x2, x3);
+ x1 = _mm512_fnmadd_round_ph (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC);
+ x1 = _mm512_mask_fnmadd_round_ph (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC);
+ x3 = _mm512_mask3_fnmadd_round_ph (x1, x2, x3, m, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC);
+ x1 = _mm512_maskz_fnmadd_round_ph (m, x1, x2, x3, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmaddXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmaddXXXph-1b.c
new file mode 100644
index 00000000000..b15b1bd1149
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmaddXXXph-1b.c
@@ -0,0 +1,159 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(fnmadd_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = -(v1.f32[i] * v3.f32[i]) + v7.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = -(v2.f32[i] * v4.f32[i]) + v8.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void NOINLINE
+EMULATE(m_fnmadd_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = -(v1.f32[i] * v7.f32[i]) + v3.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = -(v2.f32[i] * v8.f32[i]) + v4.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+TEST (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+
+ init_dest(&res, &exp);
+ EMULATE(fnmadd_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fnmadd_ph) (HF(src1), HF(src2),
+ HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fnmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fnmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fnmadd_ph) (HF(res), MASK_VALUE,
+ HF(src1), HF(src2));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fnmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fnmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fnmadd_ph) (HF(src1), HF(src2),
+ HF(res), MASK_VALUE);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fnmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fnmadd_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fnmadd_ph) (ZMASK_VALUE, HF(src1),
+ HF(src2), HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fnmadd_ph);
+
+#if AVX512F_LEN == 512
+ init_dest(&res, &exp);
+ EMULATE(fnmadd_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fnmadd_round_ph) (HF(src1), HF(src2),
+ HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fnmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fnmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fnmadd_round_ph) (HF(res), MASK_VALUE,
+ HF(src1), HF(src2), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fnmadd_ph);
+
+ EMULATE(fnmadd_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fnmadd_round_ph) (HF(src1), HF(src2),
+ HF(res), MASK_VALUE, _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fnmadd_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fnmadd_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fnmadd_round_ph) (ZMASK_VALUE, HF(src1),
+ HF(src2), HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fnmadd_ph);
+#endif
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmsubXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmsubXXXph-1a.c
new file mode 100644
index 00000000000..eb05de46347
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmsubXXXph-1a.c
@@ -0,0 +1,32 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\n\]*\{rn-sae\}\[^\{\n\]*%zmm\[0-9\]+(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\n\]*\{rd-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231ph\[ \\t\]+\[^\n\]*\{ru-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\n\]*\{rz-sae\}\[^\{\n\]*%zmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m512h x1, x2, x3;
+volatile __mmask32 m;
+
+void extern
+avx512f_test (void)
+{
+ x1 = _mm512_fnmsub_ph (x1, x2, x3);
+ x1 = _mm512_mask_fnmsub_ph (x1, m, x2, x3);
+ x3 = _mm512_mask3_fnmsub_ph (x1, x2, x3, m);
+ x1 = _mm512_maskz_fnmsub_ph (m, x1, x2, x3);
+ x1 = _mm512_fnmsub_round_ph (x1, x2, x3, _MM_FROUND_TO_NEAREST_INT
+ | _MM_FROUND_NO_EXC);
+ x1 = _mm512_mask_fnmsub_round_ph (x1, m, x2, x3, _MM_FROUND_TO_NEG_INF
+ | _MM_FROUND_NO_EXC);
+ x3 = _mm512_mask3_fnmsub_round_ph (x1, x2, x3, m, _MM_FROUND_TO_POS_INF
+ | _MM_FROUND_NO_EXC);
+ x1 = _mm512_maskz_fnmsub_round_ph (m, x1, x2, x3, _MM_FROUND_TO_ZERO
+ | _MM_FROUND_NO_EXC);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmsubXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmsubXXXph-1b.c
new file mode 100644
index 00000000000..73f0172ca20
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16-vfnmsubXXXph-1b.c
@@ -0,0 +1,157 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512dq" } */
+
+
+#define AVX512FP16
+#include "avx512fp16-helper.h"
+
+#define N_ELEMS (AVX512F_LEN / 16)
+
+void NOINLINE
+EMULATE(fnmsub_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = -(v1.f32[i] * v3.f32[i]) - v7.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = -(v2.f32[i] * v4.f32[i]) - v8.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void NOINLINE
+EMULATE(m_fnmsub_ph) (V512 * dest, V512 op1, V512 op2,
+ __mmask32 k, int zero_mask)
+{
+ V512 v1, v2, v3, v4, v5, v6, v7, v8;
+ int i;
+ __mmask16 m1, m2;
+
+ m1 = k & 0xffff;
+ m2 = (k >> 16) & 0xffff;
+
+ unpack_ph_2twops(op1, &v1, &v2);
+ unpack_ph_2twops(op2, &v3, &v4);
+ unpack_ph_2twops(*dest, &v7, &v8);
+
+ for (i = 0; i < 16; i++) {
+ if (((1 << i) & m1) == 0) {
+ if (zero_mask) {
+ v5.f32[i] = 0;
+ }
+ else {
+ v5.u32[i] = v7.u32[i];
+ }
+ }
+ else {
+ v5.f32[i] = -(v1.f32[i] * v7.f32[i]) - v3.f32[i];
+ }
+
+ if (((1 << i) & m2) == 0) {
+ if (zero_mask) {
+ v6.f32[i] = 0;
+ }
+ else {
+ v6.u32[i] = v8.u32[i];
+ }
+ }
+ else {
+ v6.f32[i] = -(v2.f32[i] * v8.f32[i]) - v4.f32[i];
+ }
+
+ }
+ *dest = pack_twops_2ph(v5, v6);
+}
+
+void
+TEST (void)
+{
+ V512 res;
+ V512 exp;
+
+ init_src();
+
+ init_dest(&res, &exp);
+ EMULATE(fnmsub_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fnmsub_ph) (HF(src1), HF(src2),
+ HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fnmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fnmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fnmsub_ph) (HF(res), MASK_VALUE,
+ HF(src1), HF(src2));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fnmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fnmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fnmsub_ph) (HF(src1), HF(src2), HF(res), MASK_VALUE);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fnmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fnmsub_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fnmsub_ph) (ZMASK_VALUE, HF(src1), HF(src2), HF(res));
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fnmsub_ph);
+
+#if AVX512F_LEN == 512
+ init_dest(&res, &exp);
+ EMULATE(fnmsub_ph)(&exp, src1, src2, NET_MASK, 0);
+ HF(res) = INTRINSIC (_fnmsub_round_ph) (HF(src1), HF(src2),
+ HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _fnmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(m_fnmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask_fnmsub_round_ph) (HF(res), MASK_VALUE,
+ HF(src1), HF(src2), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask_fnmsub_ph);
+
+ EMULATE(fnmsub_ph)(&exp, src1, src2, MASK_VALUE, 0);
+ HF(res) = INTRINSIC (_mask3_fnmsub_round_ph) (HF(src1), HF(src2),
+ HF(res), MASK_VALUE, _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _mask3_fnmsub_ph);
+
+ init_dest(&res, &exp);
+ EMULATE(fnmsub_ph)(&exp, src1, src2, ZMASK_VALUE, 1);
+ HF(res) = INTRINSIC (_maskz_fnmsub_round_ph) (ZMASK_VALUE, HF(src1),
+ HF(src2), HF(res), _ROUND_NINT);
+ CHECK_RESULT (&res, &exp, N_ELEMS, _maskz_fnmsub_ph);
+#endif
+
+ if (n_errs != 0) {
+ abort ();
+ }
+}
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddXXXph-1a.c
new file mode 100644
index 00000000000..eea38b860ae
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddXXXph-1a.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfmadd231ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd231ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmadd...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256h yy, y2, y3;
+volatile __m128h xx, x2, x3;
+volatile __mmask8 m;
+volatile __mmask16 m16;
+
+void extern
+avx512vl_test (void)
+{
+ yy = _mm256_mask_fmadd_ph (yy, m16, y2, y3);
+ xx = _mm_mask_fmadd_ph (xx, m, x2, x3);
+
+ y3 = _mm256_mask3_fmadd_ph (yy, y2, y3, m16);
+ x3 = _mm_mask3_fmadd_ph (xx, x2, x3, m);
+
+ yy = _mm256_maskz_fmadd_ph (m16, yy, y2, y3);
+ xx = _mm_maskz_fmadd_ph (m, xx, x2, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddXXXph-1b.c
new file mode 100644
index 00000000000..f6e4a9ae128
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmaddXXXph-1b.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfmaddXXXph-1b.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfmaddXXXph-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmsubXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmsubXXXph-1a.c
new file mode 100644
index 00000000000..add1abc2bea
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmsubXXXph-1a.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfmsub231ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub231ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfmsub...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256h yy, y2, y3;
+volatile __m128h xx, x2, x3;
+volatile __mmask8 m;
+volatile __mmask16 m16;
+
+void extern
+avx512vl_test (void)
+{
+ yy = _mm256_mask_fmsub_ph (yy, m16, y2, y3);
+ xx = _mm_mask_fmsub_ph (xx, m, x2, x3);
+
+ y3 = _mm256_mask3_fmsub_ph (yy, y2, y3, m16);
+ x3 = _mm_mask3_fmsub_ph (xx, x2, x3, m);
+
+ yy = _mm256_maskz_fmsub_ph (m16, yy, y2, y3);
+ xx = _mm_maskz_fmsub_ph (m, xx, x2, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmsubXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmsubXXXph-1b.c
new file mode 100644
index 00000000000..b9c2085ecd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfmsubXXXph-1b.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfmsubXXXph-1b.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfmsubXXXph-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1a.c
new file mode 100644
index 00000000000..6dad9013581
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1a.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd231ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmadd...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256h yy, y2, y3;
+volatile __m128h xx, x2, x3;
+volatile __mmask8 m;
+volatile __mmask16 m16;
+
+void extern
+avx512vl_test (void)
+{
+ yy = _mm256_mask_fnmadd_ph (yy, m16, y2, y3);
+ xx = _mm_mask_fnmadd_ph (xx, m, x2, x3);
+
+ y3 = _mm256_mask3_fnmadd_ph (yy, y2, y3, m16);
+ x3 = _mm_mask3_fnmadd_ph (xx, x2, x3, m);
+
+ yy = _mm256_maskz_fnmadd_ph (m16, yy, y2, y3);
+ xx = _mm_maskz_fnmadd_ph (m, xx, x2, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1b.c
new file mode 100644
index 00000000000..6c615d6541e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmaddXXXph-1b.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfnmaddXXXph-1b.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfnmaddXXXph-1b.c"
+
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1a.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1a.c
new file mode 100644
index 00000000000..1a7fd092b73
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1a.c
@@ -0,0 +1,28 @@
+/* { dg-do compile } */
+/* { dg-options "-mavx512vl -mavx512fp16 -O2" } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 2 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub231ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\{\n\]*%ymm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+/* { dg-final { scan-assembler-times "vfnmsub...ph\[ \\t\]+\[^\{\n\]*%xmm\[0-9\]+\{%k\[1-7\]\}\{z\}(?:\n|\[ \\t\]+#)" 1 } } */
+
+#include <immintrin.h>
+
+volatile __m256h yy, y2, y3;
+volatile __m128h xx, x2, x3;
+volatile __mmask8 m;
+volatile __mmask16 m16;
+
+void extern
+avx512vl_test (void)
+{
+ yy = _mm256_mask_fnmsub_ph (yy, m16, y2, y3);
+ xx = _mm_mask_fnmsub_ph (xx, m, x2, x3);
+
+ y3 = _mm256_mask3_fnmsub_ph (yy, y2, y3, m16);
+ x3 = _mm_mask3_fnmsub_ph (xx, x2, x3, m);
+
+ yy = _mm256_maskz_fnmsub_ph (m16, yy, y2, y3);
+ xx = _mm_maskz_fnmsub_ph (m, xx, x2, x3);
+}
diff --git a/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1b.c b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1b.c
new file mode 100644
index 00000000000..6d72b3dc220
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/avx512fp16vl-vfnmsubXXXph-1b.c
@@ -0,0 +1,15 @@
+/* { dg-do run { target avx512fp16 } } */
+/* { dg-options "-O2 -mavx512fp16 -mavx512vl -mavx512dq" } */
+
+#define AVX512VL
+#define AVX512F_LEN 256
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfnmsubXXXph-1b.c"
+
+#undef AVX512F_LEN
+#undef AVX512F_LEN_HALF
+
+#define AVX512F_LEN 128
+#define AVX512F_LEN_HALF 128
+#include "avx512fp16-vfnmsubXXXph-1b.c"
+
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2021-09-18 7:10 [gcc r12-3648] AVX512FP16: Add testcase for fma instructions hongtao Liu
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