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From: Matthew Malcomson <matmal01@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/vendors/ARM/heads/morello)] Adjust some scan-assembler directives for PureCap testsuite Date: Tue, 21 Sep 2021 09:15:41 +0000 (GMT) [thread overview] Message-ID: <20210921091541.B2EBA3858422@sourceware.org> (raw) https://gcc.gnu.org/g:1e7b5d4800013e5e53195ac16e3c35a86f2c900a commit 1e7b5d4800013e5e53195ac16e3c35a86f2c900a Author: Matthew Malcomson <matthew.malcomson@arm.com> Date: Thu Sep 16 11:34:15 2021 +0100 Adjust some scan-assembler directives for PureCap testsuite Since PureCap drastically changes how symbols are loaded, this affects some testsuite cases that search for given instructions. In this patch we: - Change gcc.dg/20021029-1.c to allow use of the REL/RO section since all .capinit entries in the indirection table use this. - Allow an extra LDR for indirection in every function of gcc.target/aarch64/struct_cpy.c - Remove the optimisation requirement in gcc.target/aarch64/vec_init_1.c since loading a constant is now indirect and we don't want to assert how a constant will be loaded through this extra indirection. Diff: --- gcc/testsuite/gcc.dg/20021029-1.c | 2 +- gcc/testsuite/gcc.target/aarch64/struct_cpy.c | 5 ++++- gcc/testsuite/gcc.target/aarch64/vec_init_1.c | 4 ++-- 3 files changed, 7 insertions(+), 4 deletions(-) diff --git a/gcc/testsuite/gcc.dg/20021029-1.c b/gcc/testsuite/gcc.dg/20021029-1.c index f11a6e4a920..717b87c60e8 100644 --- a/gcc/testsuite/gcc.dg/20021029-1.c +++ b/gcc/testsuite/gcc.dg/20021029-1.c @@ -2,7 +2,7 @@ variables into writable sections. */ /* { dg-do compile { target fpic } } */ /* { dg-options "-O2 -fpic" } */ -/* { dg-final { scan-assembler-not ".data.rel.ro.local" } } */ +/* { dg-final { scan-assembler-not ".data.rel.ro.local" { target { ! cheri_capability_pure } } } } */ /* { dg-require-effective-target label_values } */ /* { dg-require-effective-target indirect_jumps } */ diff --git a/gcc/testsuite/gcc.target/aarch64/struct_cpy.c b/gcc/testsuite/gcc.target/aarch64/struct_cpy.c index 26195971e64..2c27be9af2d 100644 --- a/gcc/testsuite/gcc.target/aarch64/struct_cpy.c +++ b/gcc/testsuite/gcc.target/aarch64/struct_cpy.c @@ -63,7 +63,10 @@ FUN(14) FUN(15) FUN(16) -/* { dg-final { scan-assembler-times {ldr\s} 18 } } */ +/* { dg-final { scan-assembler-times {ldr\s} 18 { target { ! cheri_capability_pure } } } } */ +/* For PureCap the indirection means that every function has an extra `ldr` + just to get the address to load from. 18 + 16 = 34. */ +/* { dg-final { scan-assembler-times {ldr\s} 34 { target cheri_capability_pure } } } */ /* { dg-final { scan-assembler-times {ldrb} 4 } } */ /* { dg-final { scan-assembler-times {ldrh} 4 } } */ /* { dg-final { scan-assembler-times {ldp} 1 } } */ diff --git a/gcc/testsuite/gcc.target/aarch64/vec_init_1.c b/gcc/testsuite/gcc.target/aarch64/vec_init_1.c index c8b48dac452..fdb8638f8b3 100644 --- a/gcc/testsuite/gcc.target/aarch64/vec_init_1.c +++ b/gcc/testsuite/gcc.target/aarch64/vec_init_1.c @@ -28,8 +28,8 @@ main (int argc, char **argv) /* For memory models that don't have an addend on the lane value load we can merge the load and lane insert into an LD1. For others we expect LDR + INS sequences. */ -/* { dg-final { scan-assembler-times "ld1\\t" 2 { target { aarch64_tiny || aarch64_large } } } } */ -/* { dg-final { scan-assembler-times "ins\\t" 2 { target aarch64_small } } } */ +/* { dg-final { scan-assembler-times "ld1\\t" 2 { target { { aarch64_tiny || aarch64_large } && { ! cheri_capability_pure } } } } } */ +/* { dg-final { scan-assembler-times "ins\\t" 2 { target { aarch64_small && { ! cheri_capability_pure } } } } } */ /* What we want to check, is that make_vector does not stp the whole vector to the stack. Unfortunately here we scan the body of main() too, which may be a bit fragile - the test is currently passing only because of the option
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