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* [gcc r12-3998] arm: Enable Cortex-R52+ CPU
@ 2021-09-30 22:14 Przemyslaw Wirkus
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From: Przemyslaw Wirkus @ 2021-09-30 22:14 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:cd08eae26ed23497ace5f4ee6f3a41eb5bd36c38
commit r12-3998-gcd08eae26ed23497ace5f4ee6f3a41eb5bd36c38
Author: Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
Date: Thu Sep 30 21:32:48 2021 +0100
arm: Enable Cortex-R52+ CPU
Patch is adding Cortex-R52+ as 'cortex-r52plus' command line
flag for -mcpu option.
gcc/ChangeLog:
* config/arm/arm-cpus.in: Add Cortex-R52+ CPU.
* config/arm/arm-tables.opt: Regenerate.
* config/arm/arm-tune.md: Regenerate.
* doc/invoke.texi: Update docs.
Diff:
---
gcc/config/arm/arm-cpus.in | 10 ++++++++++
gcc/config/arm/arm-tables.opt | 3 +++
gcc/config/arm/arm-tune.md | 2 +-
gcc/doc/invoke.texi | 8 ++++----
4 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/gcc/config/arm/arm-cpus.in b/gcc/config/arm/arm-cpus.in
index bcc9ebe9fe0..d0d0d0f1c7e 100644
--- a/gcc/config/arm/arm-cpus.in
+++ b/gcc/config/arm/arm-cpus.in
@@ -1612,6 +1612,16 @@ begin cpu cortex-r52
part d13
end cpu cortex-r52
+begin cpu cortex-r52plus
+ cname cortexr52plus
+ tune flags LDSCHED
+ architecture armv8-r+crc+simd
+ option nofp.dp remove FP_DBL ALL_SIMD
+ costs cortex
+ vendor 41
+ part d16
+end cpu cortex-r52plus
+
# FPU entries
# format:
# begin fpu <name>
diff --git a/gcc/config/arm/arm-tables.opt b/gcc/config/arm/arm-tables.opt
index 5692d4fb77a..8bb0c9f6a7b 100644
--- a/gcc/config/arm/arm-tables.opt
+++ b/gcc/config/arm/arm-tables.opt
@@ -282,6 +282,9 @@ Enum(processor_type) String(cortex-m55) Value( TARGET_CPU_cortexm55)
EnumValue
Enum(processor_type) String(cortex-r52) Value( TARGET_CPU_cortexr52)
+EnumValue
+Enum(processor_type) String(cortex-r52plus) Value( TARGET_CPU_cortexr52plus)
+
Enum
Name(arm_arch) Type(int)
Known ARM architectures (for use with the -march= option):
diff --git a/gcc/config/arm/arm-tune.md b/gcc/config/arm/arm-tune.md
index b9df8640654..6482833fc35 100644
--- a/gcc/config/arm/arm-tune.md
+++ b/gcc/config/arm/arm-tune.md
@@ -49,5 +49,5 @@
cortexx1,neoversen1,cortexa75cortexa55,
cortexa76cortexa55,neoversev1,neoversen2,
cortexm23,cortexm33,cortexm35p,
- cortexm55,cortexr52"
+ cortexm55,cortexr52,cortexr52plus"
(const (symbol_ref "((enum attr_tune) arm_tune)")))
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 5b016166972..718ce926aae 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -20478,8 +20478,8 @@ Permissible names are: @samp{arm7tdmi}, @samp{arm7tdmi-s}, @samp{arm710t},
@samp{cortex-a57}, @samp{cortex-a72}, @samp{cortex-a73}, @samp{cortex-a75},
@samp{cortex-a76}, @samp{cortex-a76ae}, @samp{cortex-a77},
@samp{cortex-a78}, @samp{cortex-a78ae}, @samp{cortex-a78c},
-@samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f},
-@samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
+@samp{ares}, @samp{cortex-r4}, @samp{cortex-r4f}, @samp{cortex-r5},
+@samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52}, @samp{cortex-r52plus},
@samp{cortex-m0}, @samp{cortex-m0plus}, @samp{cortex-m1}, @samp{cortex-m3},
@samp{cortex-m4}, @samp{cortex-m7}, @samp{cortex-m23}, @samp{cortex-m33},
@samp{cortex-m35p}, @samp{cortex-m55}, @samp{cortex-x1},
@@ -20563,8 +20563,8 @@ Disables the floating-point and SIMD instructions on
@item +nofp.dp
Disables the double-precision component of the floating-point instructions
-on @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52} and
-@samp{cortex-m7}.
+on @samp{cortex-r5}, @samp{cortex-r7}, @samp{cortex-r8}, @samp{cortex-r52},
+@samp{cortex-r52plus} and @samp{cortex-m7}.
@item +nosimd
Disables the SIMD (but not floating-point) instructions on
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