[gcc(refs/vendors/ARM/heads/morello)] aarch64: Fix w iterator for CADImode

[gcc(refs/vendors/ARM/heads/morello)] aarch64: Fix w iterator for CADImode

[Matthew Malcomson]

https://gcc.gnu.org/g:dbdb8dfbb6c810af83c3ed2e30edc57a05cb6294

commit dbdb8dfbb6c810af83c3ed2e30edc57a05cb6294
Author: Alex Coplan <alex.coplan@arm.com>
Date:   Wed Sep 22 21:22:03 2021 +0100

    aarch64: Fix w iterator for CADImode
    
    When the w iterator was initially extended to CADImode, there was a
    slight bodge in using the empty string for CADImode. This conveniently
    works for REG rtxes (and even does the right thing for fakecap) but
    fails for e.g. const_null (as the testcase shows: the atomic_store<mode>
    pattern runs into this, as it stands).
    
    To fix this properly, this patch adds the 'B' format specifier to
    aarch64_print_operand (for capaBility: unfortunately 'c' is already
    taken) which forces the operand to be printed as a c-register, except
    for fakecap where it emits an x-register.
    
    This fixes the bug hit by the new test and hopefully any other pattern
    using the w iterator. Other patterns may later need updating to use the
    B prefix where they expect to take const_null operands.
    
    gcc/ChangeLog:
    
            * config/aarch64/aarch64.c (aarch64_print_operand): Implement
            'B' for capaBility.
            * config/aarch64/iterators.md (w): Map CADImode -> "B".
    
    gcc/testsuite/ChangeLog:
    
            * gcc.target/aarch64/morello/atomic-store-asm.c: New test.

Diff:
---
 gcc/config/aarch64/aarch64.c                       | 45 ++++++++++++++--------
 gcc/config/aarch64/iterators.md                    |  6 +--
 .../gcc.target/aarch64/morello/atomic-store-asm.c  | 23 +++++++++++
 3 files changed, 53 insertions(+), 21 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index 4d30f91d4d7..3512cd32ba3 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -10473,6 +10473,7 @@ aarch64_reg_name (rtx reg, unsigned int delta = 0)
 
 /* Print operand X to file F in a target specific manner according to CODE.
    The acceptable formatting commands given by CODE are:
+     'B':		A capaBility register.
      'c':		An integer or symbol address without a preceding #
 			sign.
      'C':		Take the duplicated element in a vector constant
@@ -10748,26 +10749,38 @@ aarch64_print_operand (FILE *f, rtx x, int code)
       }
       break;
 
+    case 'B':
     case 'w':
     case 'x':
-      if (x == const0_rtx || CONST_NULL_P (x)
-	  || (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x)))
-	{
-	  asm_fprintf (f, "%czr", code);
-	  break;
-	}
+      {
+	/* For fake capability we never actually want to emit c-registers:
+	   having this logic here avoids having to add many special cases in the
+	   patterns.  */
+	if (TARGET_CAPABILITY_FAKE && code == 'B')
+	  code = 'x';
 
-      if (REG_P (x) && GP_REGNUM_P (REGNO (x)))
-	{
-	  asm_fprintf (f, "%c%d", code, REGNO (x) - R0_REGNUM);
-	  break;
-	}
+	const char regch = (code == 'B' ? 'c' : code);
+	const char regs[] = { regch, '\0' };
 
-      if (REG_P (x) && REGNO (x) == SP_REGNUM)
-	{
-	  asm_fprintf (f, "%ssp", code == 'w' ? "w" : "");
-	  break;
-	}
+	if (x == CONST0_RTX (GET_MODE (x))
+	    || (CONST_DOUBLE_P (x) && aarch64_float_const_zero_rtx_p (x)))
+	  {
+	    asm_fprintf (f, "%czr", regch);
+	    break;
+	  }
+
+	if (REG_P (x) && GP_REGNUM_P (REGNO (x)))
+	  {
+	    asm_fprintf (f, "%c%d", regch, REGNO (x) - R0_REGNUM);
+	    break;
+	  }
+
+	if (REG_P (x) && REGNO (x) == SP_REGNUM)
+	  {
+	    asm_fprintf (f, "%ssp", regch == 'x' ? "" : regs);
+	    break;
+	  }
+      }
 
       /* Fall through */
 
diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md
index 681888b68f2..4d53603c05d 100644
--- a/gcc/config/aarch64/iterators.md
+++ b/gcc/config/aarch64/iterators.md
@@ -918,12 +918,8 @@
 
 ;; In GPI templates, a string like "%<w>0" will expand to "%w0" in the
 ;; 32-bit version and "%x0" in the 64-bit version.
-;; MORELLO TODO Need to figure out how to handle this iterator for
-;; tlsdesc_small_advsimd_<mode> in pure capability.
-;;   First thing to check is whether that pattern is even what we want for
-;;   purecap, since there may be a different TLS approach for PureCap.
 (define_mode_attr w [(QI "w") (HI "w") (SI "w") (DI "x") (SF "s") (DF "d")
-		     (CADI "")])
+		     (CADI "B")])
 
 ; Similar to the 'w' attribute, but maps DF -> x.  The domain of this
 ; attribute is the DXC[2] iterator.  It is intended to be used with the
diff --git a/gcc/testsuite/gcc.target/aarch64/morello/atomic-store-asm.c b/gcc/testsuite/gcc.target/aarch64/morello/atomic-store-asm.c
new file mode 100644
index 00000000000..5ec3b7cd30e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/morello/atomic-store-asm.c
@@ -0,0 +1,23 @@
+/* { dg-do assemble } */
+/* { dg-additional-options "-O2 -std=c99" } */
+extern struct a { int b; } d[];
+int *e;
+long f;
+_Bool g;
+void k() {
+  enum { ad } a;
+  long b = f;
+  struct a c = d[b];
+ah:
+  a = ad;
+  int i = c.b;
+  char j[i];
+  if (g)
+    goto am;
+  for (int h = h;;)
+    if (j[h])
+      __atomic_store_n(&e, 0, 0);
+am:
+  if (a)
+    goto ah;
+}