From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id CB70C385840B; Tue, 5 Oct 2021 17:29:11 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org CB70C385840B Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work070)] Revert patches. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work070 X-Git-Oldrev: 0a4de651122984294d43f1bdae9e8517f2eee78d X-Git-Newrev: be90bb72cf8c4dddf5a9995977b50701fa1737bb Message-Id: <20211005172911.CB70C385840B@sourceware.org> Date: Tue, 5 Oct 2021 17:29:11 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 17:29:11 -0000 https://gcc.gnu.org/g:be90bb72cf8c4dddf5a9995977b50701fa1737bb commit be90bb72cf8c4dddf5a9995977b50701fa1737bb Author: Michael Meissner Date: Tue Oct 5 13:28:04 2021 -0400 Revert patches. 2021-10-05 Michael Meissner gcc/ Revert patches. * config/rs6000/constraint.md (eD): New constraint. * config/rs6000/predicates.md (easy_fp_constant): If the constant can be loaded with XXSPLTI32DX, it is easy. (easy_vector_constant_2insns): New predicate. (easy_vector_constant): If the constant can be loaded with XXSPLTI32DX, it is easy. * config/rs6000/rs6000-protos.h (xxsplti32dx_constant_immediate): New declaration. * config/rs6000/rs6000.c (xxsplti32dx_constant_immediate): New helper function. (output_vec_const_move): If the operand can be loaded with XXSPLTI32DX, split it. (rs6000_output_move_128bit): Likewise. (prefixed_xxsplti_p): Constants loaded with XXSPLTI32DX are prefixed. * config/rs6000/rs6000.md (movsf_hardfloat): Add support for constants loaded with XXSPLTI32DX. (mov_hardfloat32, FMOVE64 iterator): Likewise. (mov_hardfloat64, FMOVE64 iterator): Likewise. (movdi_internal32): Likewise. (movdi_internal64): Likewise. * config/rs6000/rs6000.opt (-mxxsplti32dx): New option. * config/rs6000/vsx.md (UNSPEC_XXSPLTI32DX_CONST): New unspec. (vsx_mov_64bit): Add support for constants loaded with XXSPLTI32DX. (vsx_mov_32bit): Likewise. (XXSPLTI32DX): New mode iterator. (splitter for XXSPLTI32DX): Add splitter for constants loaded with XXSPLTI32DX. (xxsplti32dx__first): New insns. (xxsplti32dx__second): New insns. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eD constraint. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-df-2.c: New test. * gcc.target/powerpc/vec-splat-constant-di-2.c: New test. * gcc.target/powerpc/vec-splat-constant-v2df-2.c: New test. * gcc.target/powerpc/vec-splat-constant-v2di-2.c: New test. 2021-10-04 Michael Meissner gcc/ Revert patches. * config/rs6000/constraints.md (eW): New constraint. * config/rs6000/predicates.md (easy_vector_constant_splat_word): New predicate. (easy_vector_constant): If we can use XXSPLTIW, the vector constant is easy. * config/rs6000/rs6000-protos.h (xxspltiw_constant_immediate): New declaration. * config/rs6000/rs6000.c (xxspltiw_constant_immediate): New function. (output_vec_const_move): Add support for loading up vector constants with XXSPLTIW. (prefixed_xxsplti_p): Recognize xxspltiw instructions as prefixed. * config/rs6000/rs6000.opt (-mxxspltiw): New debug switch. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for constants loaded with XXSPLTIW. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eW constraint. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-v16qi.c: New test. * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. Diff: --- gcc/config/rs6000/constraints.md | 11 -- gcc/config/rs6000/predicates.md | 166 --------------------- gcc/config/rs6000/rs6000-protos.h | 2 - gcc/config/rs6000/rs6000.c | 158 +------------------- gcc/config/rs6000/rs6000.md | 119 ++++----------- gcc/config/rs6000/rs6000.opt | 10 -- gcc/config/rs6000/vsx.md | 107 ++----------- gcc/doc/md.texi | 6 - .../gcc.target/powerpc/vec-splat-constant-df-2.c | 24 --- .../gcc.target/powerpc/vec-splat-constant-di-2.c | 38 ----- .../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 ---- .../gcc.target/powerpc/vec-splat-constant-v2df-2.c | 24 --- .../gcc.target/powerpc/vec-splat-constant-v2di-2.c | 29 ---- .../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 --------- .../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ------- .../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 -------- 16 files changed, 49 insertions(+), 852 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index f9d1d1ab446..1700657abe9 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -213,12 +213,6 @@ "A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction." (match_operand 0 "easy_fp_constant_64bit_scalar")) -;; DImode, DFmode, V2DImode, V2DFmode constant that can be loaded with 2 -;; XXSPLTI32DX instruction. -(define_constraint "eD" - "A constant that can be loaded with a pair of XXSPLTI32DX instructions." - (match_operand 0 "easy_vector_constant_2insns")) - ;; 34-bit signed integer constant (define_constraint "eI" "A signed 34-bit integer constant if prefixed instructions are supported." @@ -234,11 +228,6 @@ "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction." (match_operand 0 "easy_fp_constant_ieee128")) -;; Vector constant that can be loaded with XXSPLTIW -(define_constraint "eW" - "A vector constant that can be loaded with the XXSPLTIW instruction." - (match_operand 0 "easy_vector_constant_splat_word")) - ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index c8f0d62d75b..30e89ec79f0 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -611,11 +611,6 @@ if (easy_fp_constant_ieee128 (op, mode)) return 1; - /* If we have the ISA 3.1 XXSPLTI32DX instruction, see if the constant can be - loaded with a pair of instructions. */ - if (easy_vector_constant_2insns (op, mode)) - return 1; - /* Otherwise consider floating point constants hard, so that the constant gets pushed to memory during the early RTL phases. This has the advantage that double precision constants that can be @@ -756,161 +751,6 @@ return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode)); }) -;; Return 1 if the operand is either a DImode/DFmode scalar constant or -;; V2DImode/V2DFmode vector constant that needs 2 XXSPLTI32DX instructions to -;; load the value - -(define_predicate "easy_vector_constant_2insns" - (match_code "const_vector,vec_duplicate,const_int,const_double") -{ - /* Can we do the XXSPLTI32DX instruction? */ - if (!TARGET_XXSPLTI32DX || !TARGET_PREFIXED || !TARGET_VSX) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - /* Convert vector constant/duplicate into a scalar. */ - if (CONST_VECTOR_P (op)) - { - if (!CONST_VECTOR_DUPLICATE_P (op)) - return false; - - op = CONST_VECTOR_ELT (op, 0); - mode = GET_MODE_INNER (mode); - } - - else if (GET_CODE (op) == VEC_DUPLICATE) - { - op = XEXP (op, 0); - mode = GET_MODE_INNER (mode); - } - - if (GET_MODE_SIZE (mode) > 8) - return false; - - /* 0.0 or 0 is easy to generate. */ - if (op == CONST0_RTX (mode)) - return false; - - /* If we can load up the constant in other ways (either a single load - constant and a direct move or XXSPLTIDP), don't generate the - XXSPLTI32DX. */ - if (CONST_INT_P (op)) - return !(satisfies_constraint_I (op) - || satisfies_constraint_L (op) - || satisfies_constraint_eI (op) - || easy_fp_constant_64bit_scalar (op, mode)); - - /* For floating point, if we can use XXSPLTIDP, we don't want to - generate XXSPLTI32DX's. */ - else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode)) - return !easy_fp_constant_64bit_scalar (op, mode); - - return false; -}) - -;; Return 1 if the operand is a constant that can be loaded with the XXSPLTIW -;; instruction that loads up a 32-bit immediate and splats it into the vector. - -(define_predicate "easy_vector_constant_splat_word" - (match_code "const_vector") -{ - HOST_WIDE_INT value; - - if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTIW) - return false; - - if (!CONST_VECTOR_P (op)) - return true; - - rtx element0 = CONST_VECTOR_ELT (op, 0); - - switch (mode) - { - /* V4SImode constant vectors that have the same element are can be used - with XXSPLTIW. */ - case V4SImode: - if (!CONST_VECTOR_DUPLICATE_P (op)) - return false; - - /* Don't return true if we can use the shorter vspltisw instruction. */ - value = INTVAL (element0); - return (!EASY_VECTOR_15 (value)); - - /* V4SFmode constant vectors that have the same element are - can be used with XXSPLTIW. */ - case V4SFmode: - if (!CONST_VECTOR_DUPLICATE_P (op)) - return false; - - /* Don't return true for 0.0f, since that can be created with - xxspltib or xxlxor. */ - return (element0 != CONST0_RTX (SFmode)); - - /* V8Hmode constant vectors that have the same element are can be used - with XXSPLTIW. */ - case V8HImode: - if (CONST_VECTOR_DUPLICATE_P (op)) - { - /* Don't return true if we can use the shorter vspltish instruction. */ - value = INTVAL (element0); - if (EASY_VECTOR_15 (value)) - return false; - - return true; - } - - else - { - /* Check if all even elements are the same and all odd elements are - the same. */ - rtx element1 = CONST_VECTOR_ELT (op, 1); - - if (!CONST_INT_P (element1)) - return false; - - for (size_t i = 2; i < GET_MODE_NUNITS (V8HImode); i += 2) - if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i)) - || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1))) - return false; - - return true; - } - - /* V16QI constant vectors that have the first four elements identical to - the next set of 4 elements, and so forth can generate XXSPLTIW. */ - case V16QImode: - { - /* If we can use XXSPLTIB, don't generate XXSPLTIW. */ - if (xxspltib_constant_nosplit (op, mode)) - return false; - - rtx element1 = CONST_VECTOR_ELT (op, 1); - rtx element2 = CONST_VECTOR_ELT (op, 2); - rtx element3 = CONST_VECTOR_ELT (op, 3); - - if (!CONST_INT_P (element0) || !CONST_INT_P (element1) - || !CONST_INT_P (element2) || !CONST_INT_P (element3)) - return false; - - for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4) - if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i)) - || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1)) - || !rtx_equal_p (element2, CONST_VECTOR_ELT (op, i + 2)) - || !rtx_equal_p (element3, CONST_VECTOR_ELT (op, i + 3))) - return false; - - return true; - } - - default: - break; - } - - return false; -}) - ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. @@ -1031,12 +871,6 @@ if (easy_vector_constant_64bit_element (op, mode)) return true; - if (easy_vector_constant_splat_word (op, mode)) - return true; - - if (easy_vector_constant_2insns (op, mode)) - return 1; - if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index f517624cc56..a21fa08b367 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -32,9 +32,7 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, extern int easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); -extern void xxsplti32dx_constant_immediate (rtx, machine_mode, long *, long *); extern long xxspltidp_constant_immediate (rtx, machine_mode); -extern long xxspltiw_constant_immediate (rtx, machine_mode); extern int lxvkq_constant_immediate (rtx, machine_mode); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index f5ca8eb1703..81004d9a879 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6939,6 +6939,11 @@ xxspltib_constant_p (rtx op, else if (IN_RANGE (value, -1, 0)) *num_insns_ptr = 1; + /* See if we could generate the constant with XXSPLTIW instead of XXSPLTIB + + VUPKLSB/VEXTSB2W. */ + else if ((mode == V8HImode || mode == V4SImode) && TARGET_POWER10 && TARGET_XXSPLTIW) + return false; + else *num_insns_ptr = 2; @@ -6946,59 +6951,6 @@ xxspltib_constant_p (rtx op, return true; } -/* Return the two 32-bit constants to use in the two XXSPLTI32DX instructions - via HIGH_PTR and LOW_PTR. */ - -void -xxsplti32dx_constant_immediate (rtx op, - machine_mode mode, - long *high_ptr, - long *low_ptr) -{ - gcc_assert (easy_vector_constant_2insns (op, mode)); - - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (CONST_VECTOR_P (op)) - { - op = CONST_VECTOR_ELT (op, 0); - mode = GET_MODE_INNER (mode); - } - - else if (GET_CODE (op) == VEC_DUPLICATE) - { - op = XEXP (op, 0); - mode = GET_MODE_INNER (mode); - } - - if (CONST_INT_P (op)) - { - HOST_WIDE_INT value = INTVAL (op); - *high_ptr = (value >> 32) & 0xffffffff; - *low_ptr = value & 0xffffffff; - return; - } - - else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode)) - { - long high_low[2]; - const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op); - REAL_VALUE_TO_TARGET_DOUBLE (*rv, high_low); - - /* The double precision value is laid out in memory order. We need to - undo this for XXSPLTI32DX. */ - if (!BYTES_BIG_ENDIAN) - std::swap (high_low[0], high_low[1]); - - *high_ptr = high_low[0] & 0xffffffff; - *low_ptr = high_low[1] & 0xffffffff; - return; - } - - gcc_unreachable (); -} - /* Return the immediate value used in the XXSPLTIDP instruction. */ long @@ -7053,82 +7005,6 @@ xxspltidp_constant_immediate (rtx op, machine_mode mode) return ret; } -/* Return the immediate value used in the XXSPLTIW instruction. */ -long -xxspltiw_constant_immediate (rtx op, machine_mode mode) -{ - long ret; - - gcc_assert (easy_vector_constant_splat_word (op, mode)); - - switch (mode) - { - default: - gcc_unreachable (); - - /* V4SImode constant vectors that have the same element are can be used - with XXSPLTIW. */ - case E_V4SImode: - gcc_assert (CONST_VECTOR_DUPLICATE_P (op)); - ret = INTVAL (CONST_VECTOR_ELT (op, 0)); - break; - - /* V4SFmode constant vectors that have the same element are - can be used with XXSPLTIW. */ - case E_V4SFmode: - gcc_assert (CONST_VECTOR_DUPLICATE_P (op)); - ret = rs6000_const_f32_to_i32 (CONST_VECTOR_ELT (op, 0)); - break; - - /* V8HImode constant vectors with all of the even elements the same and - all of the odd elements the same can used XXSPLTIW. */ - case E_V8HImode: - { - if (!rtx_equal_p (CONST_VECTOR_ELT (op, 0), CONST_VECTOR_ELT (op, 2)) - || !rtx_equal_p (CONST_VECTOR_ELT (op, 1), CONST_VECTOR_ELT (op, 3))) - gcc_unreachable (); - - long value0 = INTVAL (CONST_VECTOR_ELT (op, 0)) & 0xffff; - long value1 = INTVAL (CONST_VECTOR_ELT (op, 1)) & 0xffff; - - if (!BYTES_BIG_ENDIAN) - std::swap (value0, value1); - - ret = (value0 << 16) | value1; - } - break; - - /* V16QI constant vectors that have the first four elements identical to - the next set of 4 elements, and so forth can generate XXSPLTIW. */ - case E_V16QImode: - { - rtx op0 = CONST_VECTOR_ELT (op, 0); - rtx op1 = CONST_VECTOR_ELT (op, 1); - rtx op2 = CONST_VECTOR_ELT (op, 2); - rtx op3 = CONST_VECTOR_ELT (op, 3); - - for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4) - if (!rtx_equal_p (op0, CONST_VECTOR_ELT (op, i)) - || !rtx_equal_p (op1, CONST_VECTOR_ELT (op, i + 1)) - || !rtx_equal_p (op2, CONST_VECTOR_ELT (op, i + 2)) - || !rtx_equal_p (op3, CONST_VECTOR_ELT (op, i + 3))) - gcc_unreachable (); - - long value0 = INTVAL (op0) & 0xff; - long value1 = INTVAL (op1) & 0xff; - long value2 = INTVAL (op2) & 0xff; - long value3 = INTVAL (op3) & 0xff; - - ret = ((BYTES_BIG_ENDIAN) - ? ((value0 << 24) | (value1 << 16) | (value2 << 8) | value3) - : ((value3 << 24) | (value2 << 16) | (value1 << 8) | value0)); - } - break; - } - - return ret; -} - /* Return the constant that will go in the LXVKQ instruction. */ /* LXVKQ immediates. */ @@ -7270,21 +7146,12 @@ output_vec_const_move (rtx *operands) return "xxspltidp %x0,%2"; } - if (easy_vector_constant_splat_word (vec, mode)) - { - operands[2] = GEN_INT (xxspltiw_constant_immediate (vec, mode)); - return "xxspltiw %x0,%2"; - } - if (easy_fp_constant_ieee128 (vec, mode)) { operands[2] = GEN_INT (lxvkq_constant_immediate (vec, mode)); return "lxvkq %x0,%2"; } - if (easy_vector_constant_2insns (vec, mode)) - return "#"; - if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -14133,9 +14000,6 @@ rs6000_output_move_128bit (rtx operands[]) return "lxvkq %x0,%2"; } - else if (dest_vsx_p && easy_vector_constant_2insns (src, mode)) - return "#"; - else if (dest_regno >= 0 && (CONST_INT_P (src) || CONST_WIDE_INT_P (src) @@ -27050,19 +26914,11 @@ prefixed_xxsplti_p (rtx_insn *insn) case E_DImode: case E_DFmode: case E_SFmode: - return (easy_fp_constant_64bit_scalar (src, mode) - || easy_vector_constant_2insns (src, mode)); + return easy_fp_constant_64bit_scalar (src, mode); case E_V2DImode: case E_V2DFmode: - return (easy_vector_constant_64bit_element (src, mode) - || easy_vector_constant_2insns (src, mode)); - - case E_V16QImode: - case E_V8HImode: - case E_V4SImode: - case E_V4SFmode: - return easy_vector_constant_splat_word (src, mode); + return easy_vector_constant_64bit_element (src, mode); default: break; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 5c120ef1672..8afc4b2756d 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -7764,17 +7764,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT MF NOP XXSPLTIDP XXSPLTI32DX +;; MR MT MF NOP XXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h, wa, wa") + !r, *c*l, !r, *h, wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0, eF, eD"))] + r, r, *h, 0, eF"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7797,24 +7797,15 @@ mt%0 %1 mf%1 %0 nop - # #" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *, vecperm, vecperm") + *, mtjmpr, mfjmpr, *, vecperm") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *, p10, p10") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *, *, *, 2") - (set_attr "num_insns" - "*, *, *, *, *, *, - *, *, *, *, *, *, - *, *, *, *, *, 2")]) + *, *, *, *, p10")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -8074,18 +8065,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR XXSPLTIDP XXSPLTI32DX +;; LWZ STW MR XXSPLTIDP (define_insn "*mov_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, - Y, r, !r, wa, wa") + Y, r, !r, wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , - r, Y, r, eF, eD"))] + r, Y, r, eF"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8103,29 +8094,20 @@ # # # - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two, vecperm, vecperm") + store, load, two, vecperm") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8, *, *") - (set_attr "num_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2") + 8, 8, 8, *") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *, p10, p10")]) + *, *, *, p10")]) ;; STW LWZ MR G-const H-const F-const @@ -8152,19 +8134,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFVSRD MTVSRD XXSPLTIDP XXSPLTI32DX +;; NOP MFVSRD MTVSRD XXSPLTIDP (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, YZ, r, !r, *c*l, !r, - *h, r, , wa, wa") + *h, r, , wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, YZ, r, r, *h, - 0, , r, eF, eD"))] + 0, , r, eF"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8187,29 +8169,18 @@ nop mfvsrd %0,%x1 mtvsrd %x0,%1 - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr, vecperm, vecperm") + *, mfvsr, mtvsr, vecperm") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, *, *, *, *, *, - *, p8v, p8v, p10, p10") - (set_attr "num_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, - *, *, *, *, *, - *, *, *, *, *, - *, *, *, *, 2")]) + *, p8v, p8v, p10")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special @@ -9257,7 +9228,7 @@ ;; a gpr into a fpr instead of reloading an invalid 'Y' address ;; GPR store GPR load GPR move FPR store FPR load FPR move -;; XXSPLTIDP XXSPLTI32DX +;; XXSPLTIDP ;; GPR const AVX store AVX store AVX load AVX load VSX move ;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const ;; AVX const @@ -9265,13 +9236,13 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, m, ^d, ^d, - ^wa, ^wa, + ^wa, r, wY, Z, ^v, $v, ^wa, wa, wa, v, wa, *i, v, v") (match_operand:DI 1 "input_operand" "r, Y, r, ^d, m, ^d, - eF, eD, + eF, IJKnF, ^v, $v, wY, Z, ^wa, Oj, wM, OjwM, Oj, wM, wS, wB"))] @@ -9287,7 +9258,6 @@ fmr %0,%1 # # - # stxsd %1,%0 stxsdx %x1,%y0 lxsd %0,%1 @@ -9302,32 +9272,20 @@ #" [(set_attr "type" "store, load, *, fpstore, fpload, fpsimple, - vecperm, vecperm, + vecperm, *, fpstore, fpstore, fpload, fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple, vecsimple") (set_attr "size" "64") (set_attr "length" "8, 8, 8, *, *, *, - *, *, + *, 16, *, *, *, *, *, *, *, *, *, *, 8, *") - (set_attr "num_insns" - "*, *, *, *, *, *, - *, *, - *, *, *, *, *, *, - *, *, *, *, *, *, - *") - (set_attr "max_prefixed_insns" - "*, *, *, *, *, *, - *, *, - *, *, *, *, *, *, - *, *, *, *, *, *, - *") (set_attr "isa" "*, *, *, *, *, *, - p10, p10, + p10, *, p9v, p7v, p9v, p7v, *, p9v, p9v, p7v, *, *, p7v, p7v")]) @@ -9363,7 +9321,7 @@ }) ;; GPR store GPR load GPR move -;; XXSPLTIDP XXSPLTI32DX +;; XXSPLTIDP ;; GPR li GPR lis GPR pli GPR # ;; FPR store FPR load FPR move ;; AVX store AVX store AVX load AVX load VSX move @@ -9374,7 +9332,7 @@ (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, - ^wa, ^wa, + ^wa, r, r, r, r, m, ^d, ^d, wY, Z, $v, $v, ^wa, @@ -9384,7 +9342,7 @@ ?r, ?wa") (match_operand:DI 1 "input_operand" "r, YZ, r, - eF, eD, + eF, I, L, eI, nF, ^d, m, ^d, ^v, $v, wY, Z, ^wa, @@ -9400,7 +9358,6 @@ ld%U1%X1 %0,%1 mr %0,%1 # - # li %0,%1 lis %0,%v1 li %0,%1 @@ -9427,7 +9384,7 @@ mtvsrd %x0,%1" [(set_attr "type" "store, load, *, - vecperm, vecperm, + vecperm, *, *, *, *, fpstore, fpload, fpsimple, fpstore, fpstore, fpload, fpload, veclogical, @@ -9438,7 +9395,7 @@ (set_attr "size" "64") (set_attr "length" "*, *, *, - *, *, + *, *, *, *, 20, *, *, *, *, *, *, *, *, @@ -9446,29 +9403,9 @@ 8, *, *, *, *, *, *") - (set_attr "num_insns" - "*, *, *, - *, 2, - *, *, *, *, - *, *, *, - *, *, *, *, *, - *, *, *, *, *, - 8, *, - *, *, *, - *, *") - (set_attr "max_prefixed_insns" - "*, *, *, - *, 2, - *, *, *, *, - *, *, *, - *, *, *, *, *, - *, *, *, *, *, - 8, *, - *, *, *, - *, *") (set_attr "isa" "*, *, *, - p10, p10, + p10, *, *, p10, *, *, *, *, p9v, p7v, p9v, p7v, *, diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 898bc4e9e6e..c9eb78952d6 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -640,20 +640,10 @@ mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. -;; Do not enable at this time. -mxxsplti32dx -Target Undocumented Var(TARGET_XXSPLTI32DX) Init(0) Save -Generate (do not generate) XXSPLTI32DX instructions. - mxxspltidp Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save Generate (do not generate) XXSPLTIDP instructions. -;; Do not enable at this time. -mxxspltiw -Target Undocumented Var(TARGET_XXSPLTIW) Init(0) Save -Generate (do not generate) XXSPLTIW instructions. - mlxvkq Target Undocumented Var(TARGET_LXVKQ) Init(1) Save Generate (do not generate) LXVKQ instructions. diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index cc21c454491..d7e58654ded 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -376,7 +376,6 @@ UNSPEC_XXSPLTIW UNSPEC_XXSPLTIDP UNSPEC_XXSPLTI32DX - UNSPEC_XXSPLTI32DX_CONST UNSPEC_XXBLEND UNSPEC_XXPERMX ]) @@ -1192,19 +1191,19 @@ ;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move. ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) -;; XXSPLTIDP XXSPLTIW LXVKQ XXSPLTI32DX +;; XXSPLTIDP LXVKQ ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, - wa, wa, wa, wa, + wa, wa, ?&r, ??r, ??Y, , wa, v, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, - eV, eW, eQ, eD, + eV, eQ, wQ, Y, r, r, wE, jwM, ?jwM, W, , v, wZ"))] @@ -1216,44 +1215,44 @@ } [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, - vecperm, vecperm, vecperm, vecperm, + vecperm, vecperm, store, load, store, *, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") (set_attr "num_insns" "*, *, *, 2, *, 2, - *, *, *, 2, + *, *, 2, 2, 2, 2, *, *, *, 5, 2, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, - *, *, *, 2, + *, *, 2, 2, 2, 2, *, *, *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, - *, *, *, *, + *, *, 8, 8, 8, 8, *, *, *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, - p10, p10, p10, p10, + p10, p10, *, *, *, *, p9v, *, , *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move -;; XXSPLTIDP XXSPLTIW LXVKQ XXSPLTI32DX +;; XXSPLTIDP LXVKQ ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const ;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , - wa, wa, wa, wa, + wa, wa, wa, v, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, - eV, eW, eQ, eD, + eV, eQ, wE, jwM, ?jwM, W, , v, wZ"))] @@ -1265,27 +1264,17 @@ } [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, - vecperm, vecperm, vecperm, vecperm, + vecperm, vecperm, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, - *, *, *, *, + *, *, *, *, *, 20, 16, *, *") - (set_attr "num_insns" - "*, *, *, *, *, *, - *, *, *, 2, - *, *, *, *, *, - *, *") - (set_attr "length" - "*, *, *, *, *, *, - *, *, *, 2, - *, *, *, *, *, - *, *") (set_attr "isa" ", , , *, *, *, - p10, p10, p10, p10, + p10, p10, p9v, *, , *, *, *, *")]) @@ -6581,74 +6570,6 @@ [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) -;; XXSPLTI32DX used to create 64-bit constants or vector constants where the -;; even elements match and the odd elements match. -(define_mode_iterator XXSPLTI32DX [DI SF DF V2DF V2DI]) - -;; Don't split DImode before register allocation, so that it has a better -;; chance of winding up in a GPR register. -(define_split - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand") - (match_operand:XXSPLTI32DX 1 "easy_vector_constant_2insns"))] - "TARGET_POWER10 && (reload_completed || mode != DImode)" - [(set (match_dup 0) - (unspec:XXSPLTI32DX [(match_dup 2) - (match_dup 3)] UNSPEC_XXSPLTI32DX_CONST)) - (set (match_dup 0) - (unspec:XXSPLTI32DX [(match_dup 0) - (match_dup 4) - (match_dup 5)] UNSPEC_XXSPLTI32DX_CONST))] -{ - long high = 0, low = 0; - - xxsplti32dx_constant_immediate (operands[1], mode, &high, &low); - - /* If the low bits are 0 or all 1s, initialize that word first. This way we - can use a smaller XXSPLTIB/XXLXOR/XXLORC instruction instead the first - XXSPLTI32DX. */ - if (low == 0 || low == -1) - { - operands[2] = const1_rtx; - operands[3] = GEN_INT (low); - operands[4] = const0_rtx; - operands[5] = GEN_INT (high); - } - else - { - operands[2] = const0_rtx; - operands[3] = GEN_INT (high); - operands[4] = const1_rtx; - operands[5] = GEN_INT (low); - } -}) - -;; First word of XXSPLTI32DX -(define_insn "*xxsplti32dx__first" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa,wa,wa") - (unspec:XXSPLTI32DX [(match_operand 1 "u1bit_cint_operand" "n,n,n") - (match_operand 2 "const_int_operand" "O,wM,n")] - UNSPEC_XXSPLTI32DX_CONST))] - "TARGET_XXSPLTI32DX" - "@ - xxlxor %x0,%x0,%x0 - xxlorc %x0,%x0,%x0 - xxsplti32dx %x0,%1,%2" - [(set_attr "type" "veclogical,veclogical,vecperm") - (set_attr "prefixed" "*,*,yes")]) - -;; Second word of XXSPLTI32DX -(define_insn "*xxsplti32dx__second" - [(set (match_operand:XXSPLTI32DX 0 "vsx_register_operand" "=wa") - (unspec:XXSPLTI32DX [(match_operand:XXSPLTI32DX 1 "vsx_register_operand" "0") - (match_operand 2 "u1bit_cint_operand" "n") - (match_operand 3 "const_int_operand" "n")] - UNSPEC_XXSPLTI32DX_CONST))] - "TARGET_XXSPLTI32DX" - "xxsplti32dx %x0,%2,%3" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - - ;; XXBLEND built-in function support (define_insn "xxblend_" [(set (match_operand:VM3 0 "register_operand" "=wa") diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index feaa205291a..813d6316d8c 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3333,9 +3333,6 @@ The integer constant zero. A constant whose negation is a signed 16-bit constant. @end ifset -@item eD -A constant that can be loaded with a pair of XXSPLTI32DX instructions. - @item eF A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction. @@ -3348,9 +3345,6 @@ An IEEE 128-bit constant that can be loaded with the LXVKQ instruction. @item eV A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction. -@item eW -A vector constant that can be loaded with the XXSPLTIW instruction. - @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c deleted file mode 100644 index 34ec3caa594..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df-2.c +++ /dev/null @@ -1,24 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */ - -#define M_PI 3.14159265358979323846 -#define SUBNORMAL 0x1p-149f - -/* Test generation of floating point constants with XXSPLTI32DX. */ - -double -df_double_pi (void) -{ - return M_PI; /* 2x XXSPLTI32DX. */ -} - -/* This float subnormal cannot be loaded with XXSPLTIDP. */ - -double -v2df_double_denorm (void) -{ - return SUBNORMAL; /* XXLXOR, XXSPLTI32DX. */ -} - -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c deleted file mode 100644 index 41b1d703fe7..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-di-2.c +++ /dev/null @@ -1,38 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */ - -/* Test generation of integer constants loaded into the vector registers with - the ISA 3.1 (power10) instruction XXSPLTI32DX. We use asm to force the - value into vector registers. */ - -#define LARGE_BITS 0x12345678ABCDEF01LL -#define SUBNORMAL 0x8000000000000001LL - -/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can - be generated with XXSPLTI32DX but not XXSLTIDP. */ -double -scalar_float_subnormal (void) -{ - /* 2x XXSPLTI32DX. */ - double d; - long long ll = SUBNORMAL; - - __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll)); - return d; -} - -/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x - XXSPLTI32DX instructions. */ -double -scalar_large_constant (void) -{ - /* 2x XXSPLTI32DX. */ - double d; - long long ll = LARGE_BITS; - - __asm__ ("xxmr %x0,%x1" : "=wa" (d) : "wa" (ll)); - return d; -} - -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c deleted file mode 100644 index 2707d86e6fd..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V16HI vector constants where the - first 4 elements are the same as the next 4 elements, etc. */ - -vector unsigned char -v16qi_const_1 (void) -{ - return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */ -} - -vector unsigned char -v16qi_const_2 (void) -{ - return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4, - 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c deleted file mode 100644 index 3f7b0a00655..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df-2.c +++ /dev/null @@ -1,24 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */ - -#define M_PI 3.14159265358979323846 -#define SUBNORMAL 0x1p-149f - -/* Test generation of floating point constants with XXSPLTI32DX. */ - -vector double -v2df_double_pi (void) -{ - /* 2x XXSPLTI32DX. */ - return (vector double) { M_PI, M_PI }; -} - -vector double -v2df_double_denorm (void) -{ - /* XXLXOR, XXSPLTI32DX. */ - return (vector double) { SUBNORMAL, SUBNORMAL }; -} - -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c deleted file mode 100644 index 90027378012..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di-2.c +++ /dev/null @@ -1,29 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxsplti32dx" } */ - -/* Test generation of integer constants loaded into the vector registers with - the ISA 3.1 (power10) instruction XXSPLTI32DX. */ - -#define LARGE_BITS 0x12345678ABCDEF01LL -#define SUBNORMAL 0x8000000000000001LL - -/* 0x8000000000000001LL is the bit pattern for a negative subnormal value can - be generated with XXSPLTI32DX but not XXSLTIDP. */ -vector long long -vector_float_subnormal (void) -{ - /* 2x XXSPLTI32DX. */ - return (vector long long) { SUBNORMAL, SUBNORMAL }; -} - -/* 0x12345678ABCDEF01LL is a large constant that can be loaded with 2x - XXSPLTI32DX instructions. */ -vector long long -vector_large_constant (void) -{ - /* 2x XXSPLTI32DX. */ - return (vector long long) { LARGE_BITS, LARGE_BITS }; -} - -/* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 4 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c deleted file mode 100644 index 05d4ee3f5cb..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c +++ /dev/null @@ -1,67 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V4SF vector constants. */ - -vector float -v4sf_const_1 (void) -{ - return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_nan (void) -{ - return (vector float) { __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf ("") }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_inf (void) -{ - return (vector float) { __builtin_inff (), - __builtin_inff (), - __builtin_inff (), - __builtin_inff () }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_m0 (void) -{ - return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */ -} - -vector float -v4sf_splats_1 (void) -{ - return vec_splats (1.0f); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_nan (void) -{ - return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_inf (void) -{ - return vec_splats (__builtin_inff ()); /* XXSPLTIW. */ -} - -vector float -v8hi_splats_m0 (void) -{ - return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */ -/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c deleted file mode 100644 index da909e948b2..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure - the power9 support (XXSPLTIB/VEXTSB2W) is not done. */ - -vector int -v4si_const_1 (void) -{ - return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */ -} - -vector int -v4si_const_126 (void) -{ - return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector int -v4si_const_1023 (void) -{ - return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector int -v4si_splats_1 (void) -{ - return vec_splats (1); /* VSLTPISW. */ -} - -vector int -v4si_splats_126 (void) -{ - return vec_splats (126); /* XXSPLTIW. */ -} - -vector int -v8hi_splats_1023 (void) -{ - return vec_splats (1023); /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c deleted file mode 100644 index 290e05d4a64..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c +++ /dev/null @@ -1,62 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure - the power9 support (XXSPLTIB/VUPKLSB) is not done. */ - -vector short -v8hi_const_1 (void) -{ - return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */ -} - -vector short -v8hi_const_126 (void) -{ - return (vector short) { 126, 126, 126, 126, - 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector short -v8hi_const_1023 (void) -{ - return (vector short) { 1023, 1023, 1023, 1023, - 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1 (void) -{ - return vec_splats ((short)1); /* VSLTPISH. */ -} - -vector short -v8hi_splats_126 (void) -{ - return vec_splats ((short)126); /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1023 (void) -{ - return vec_splats ((short)1023); /* XXSPLTIW. */ -} - -/* Test that we can optimiza V8HI where all of the even elements are the same - and all of the odd elements are the same. */ -vector short -v8hi_const_1023_1000 (void) -{ - return (vector short) { 1023, 1000, 1023, 1000, - 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */ -/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */