From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 790803858433; Tue, 5 Oct 2021 21:33:28 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 790803858433 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work070)] Revert patches. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work070 X-Git-Oldrev: 42d874113da9a4434bf7ee0eff9c12df134f2c62 X-Git-Newrev: d7d72285470faa875a443b9a701891608a81d4dc Message-Id: <20211005213328.790803858433@sourceware.org> Date: Tue, 5 Oct 2021 21:33:28 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 05 Oct 2021 21:33:28 -0000 https://gcc.gnu.org/g:d7d72285470faa875a443b9a701891608a81d4dc commit d7d72285470faa875a443b9a701891608a81d4dc Author: Michael Meissner Date: Tue Oct 5 17:32:07 2021 -0400 Revert patches. 2021-10-05 Michael Meissner gcc/ Revert patches. * config/rs6000/constraints.md (eW): New constraint. * config/rs6000/predicates.md (easy_vector_constant_splat_word): New predicate. (easy_vector_constant): If we can use XXSPLTIW, the vector constant is easy. * config/rs6000/rs6000-protos.h (xxspltiw_constant_immediate): New declaration. * config/rs6000/rs6000.c (xxspltib_constant_p): Don't return true if we could generate XXSPLTIW instead of XXSPLTIB and sign extend. (xxspltiw_constant_immediate): New function. (output_vec_const_move): Add support for loading up vector constants with XXSPLTIW. (prefixed_xxsplti_p): Recognize xxspltiw instructions as prefixed. * config/rs6000/rs6000.opt (-mxxspltiw): New debug switch. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for constants loaded with XXSPLTIW. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eW constraint. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-v16qi.c: New test. * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn regex for power10. 2021-10-05 Michael Meissner gcc/ Revert patches. * config/rs6000/constraints.md (eQ): New constraint. * config/rs6000/predicates.md (easy_fp_constant): If we can use LXVKQ, it is an easy floating point constant. (easy_fp_constant_ieee128): New predicate. * config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate): New declaration. * config/rs6000/rs6000.c (xxspltidp_constant_immediate): New function. (output_vec_const_move): Add support for LXVKQ. (rs6000_output_move_128bit): Likewise. * config/rs6000/rs6000.opt (-mlxvkq): New debug option. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for LXVKQ. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eQ constraint. gcc/testsuite/ Revert patches. * gcc.target/powerpc/float128-constant.c: New test. 2021-10-05 Michael Meissner gcc/ Revert patches. * config/rs6000/constraints.md (eF): New constraint. (eV): New constraint. * config/rs6000/predicates.md (easy_fp_constant): If we can load the scalar constant with XXSPLTIDP, the constant is easy. (easy_fp_constant_64bit_scalar): New predicate. (easy_vector_constant_64bit_element): New predicate. (easy_vector_constant): If we can generate XXSPLTIDP, mark the vector constant as easy. * config/rs6000/rs6000-protos.h (xxspltidp_constant_immediate): New declaration. (prefixed_xxsplti_p): Likewise. * config/rs6000/rs6000.c (xxspltidp_constant_immediate): New function. (output_vec_const_move): Add support for XXSPLTIDP. (prefixed_xxsplti_p): New function. * config/rs6000/rs6000.md (prefixed attribute): Add support for the xxsplti* prefixed instructions. (movsf_hardfloat): Add XXSPLTIDP support. (mov_hardfloat32, FMOVE64 iterator): Likewise. (mov_hardfloat64, FMOVE64 iterator): Likewise. (movdi_internal32): Likewise. (movdi_internal64): Likewise. * config/rs6000/rs6000.opt (-mxxspltidp): New switch. * config/rs6000/vsx.md (vsx_move_64bit): Add XXSPLTIDP support. (vsx_move_32bit): Likewise. (XXSPLTIDP_S): New mode iterator. (XXSPLTIDP_V): Likewise. (XXSPLTIDP): Likewise. (xxspltidp__inst): Replace xxspltidp_v2df_inst with an iterated form that also does SFmode, DFmode, DImode, and V2DImode. (xxspltidp__internal): New insn and splits. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eF and eV constraints. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-df.c: New test. * gcc.target/powerpc/vec-splat-constant-di.c: New test. * gcc.target/powerpc/vec-splat-constant-sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v2df.c: New test. * gcc.target/powerpc/vec-splat-constant-v2di.c: New test. * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn regex for power10. Diff: --- gcc/config/rs6000/constraints.md | 20 -- gcc/config/rs6000/predicates.md | 319 --------------------- gcc/config/rs6000/rs6000-protos.h | 4 - gcc/config/rs6000/rs6000.c | 291 ------------------- gcc/config/rs6000/rs6000.md | 58 ++-- gcc/config/rs6000/rs6000.opt | 13 - gcc/config/rs6000/vsx.md | 60 +--- gcc/doc/md.texi | 12 - .../gcc.target/powerpc/float128-constant.c | 144 ---------- .../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 -- .../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ----- .../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---- .../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 ---- 13 files changed, 22 insertions(+), 1106 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 46daeb0861c..c8cff1a3038 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -208,31 +208,11 @@ (and (match_code "const_int") (match_test "((- (unsigned HOST_WIDE_INT) ival) + 0x8000) < 0x10000"))) -;; DI/SF/DF scalar constant that can be loaded with the XXSPLTIDP instruction. -(define_constraint "eF" - "A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction." - (match_operand 0 "easy_fp_constant_64bit_scalar")) - ;; 34-bit signed integer constant (define_constraint "eI" "A signed 34-bit integer constant if prefixed instructions are supported." (match_operand 0 "cint34_operand")) -;; V2DI/V2DF vector constant that can be loaded with the XXSPLTIDP instruction. -(define_constraint "eV" - "A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction." - (match_operand 0 "easy_vector_constant_64bit_element")) - -;; KF/TF scalar than can be loaded with LXVKQ -(define_constraint "eQ" - "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction." - (match_operand 0 "easy_fp_constant_ieee128")) - -;; Vector constant that can be loaded with XXSPLTIW -(define_constraint "eW" - "A vector constant that can be loaded with the XXSPLTIW instruction." - (match_operand 0 "easy_vector_constant_splat_word")) - ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 9b9f5934e58..956e42bc514 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -601,16 +601,6 @@ if (TARGET_VSX && op == CONST0_RTX (mode)) return 1; - /* If we have the ISA 3.1 XXSPLTIDP instruction, see if the constant can - be loaded with that instruction. */ - if (easy_fp_constant_64bit_scalar (op, mode)) - return 1; - - /* If we have the ISA 3.1 LXVKQ instruction, see if the constant can be loaded - with that instruction. */ - if (easy_fp_constant_ieee128 (op, mode)) - return 1; - /* Otherwise consider floating point constants hard, so that the constant gets pushed to memory during the early RTL phases. This has the advantage that double precision constants that can be @@ -619,236 +609,6 @@ return 0; }) -;; Return 1 if the operand is a 64-bit scalar constant that can be loaded via -;; the XXSPLTIDP instruction, which takes a SFmode value and produces a V2DF or -;; V2DI mode result that is interpretted as a 64-bit scalar. -(define_predicate "easy_fp_constant_64bit_scalar" - (match_code "const_int,const_double") -{ - const REAL_VALUE_TYPE *rv; - REAL_VALUE_TYPE rv_type; - - /* Can we do the XXSPLTIDP instruction? */ - if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - /* Don't return true for 0.0 or 0 since that is easy to create without - XXSPLTIDP. */ - if (op == CONST0_RTX (mode)) - return false; - - /* Handle DImode by creating a DF value from it. */ - if (CONST_INT_P (op) && (mode == DImode || mode == VOIDmode)) - { - HOST_WIDE_INT df_value = INTVAL (op); - - /* Avoid values that look like DFmode NaN's. The IEEE 754 64-bit - floating format has 1 bit for sign, 11 bits for the exponent, - and 52 bits for the mantissa. NaN values have the exponent set - to all 1 bits, and the mantissa non-zero (mantissa == 0 is - infinity). */ - int df_exponent = (df_value >> 52) & 0x7ff; - HOST_WIDE_INT df_mantissa = df_value & HOST_WIDE_INT_C (0x1fffffffffffff); - - if (df_exponent == 0x7ff && df_mantissa != 0) /* NaN. */ - return false; - - /* Avoid values that are DFmode subnormal values. Subnormal numbers - have the exponent all 0 bits, and the mantissa non-zero. If the - value is subnormal, then the hidden bit in the mantissa is not - set. */ - if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */ - return false; - - long df_words[2]; - df_words[0] = (df_value >> 32) & 0xffffffff; - df_words[1] = df_value & 0xffffffff; - - /* real_from_target takes the target words in target order. */ - if (!BYTES_BIG_ENDIAN) - std::swap (df_words[0], df_words[1]); - - real_from_target (&rv_type, df_words, DFmode); - rv = &rv_type; - } - - /* Handle SFmode/DFmode constants. Don't allow decimal or IEEE 128-bit - binary constants. */ - else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode)) - rv = CONST_DOUBLE_REAL_VALUE (op); - - /* We can't handle anything else with the XXSPLTIDP instruction. */ - else - return false; - - /* Validate that the number can be stored as a SFmode value. */ - if (!exact_real_truncate (SFmode, rv)) - return false; - - /* Validate that the number is not a SFmode subnormal value (exponent is 0, - mantissa field is non-zero) which is undefined for the XXSPLTIDP - instruction. */ - long sf_value; - real_to_target (&sf_value, rv, SFmode); - - /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent, - and 23 bits for the mantissa. Subnormal numbers have the exponent all - 0 bits, and the mantissa non-zero. */ - long sf_exponent = (sf_value >> 23) & 0xFF; - long sf_mantissa = sf_value & 0x7FFFFF; - - if (sf_exponent == 0 && sf_mantissa != 0) - return false; - - return true; -}) - -;; Return 1 if the operand is a 64-bit vector constant that can be loaded via -;; the XXSPLTIDP instruction, which takes a SFmode value and produces a -;; V2DFmode or V2DI result. -;; -;; We cannot combine the scalar and vector cases because otherwise it is -;; problematical if we assign an appropriate integer constant to a TImode -;; value. I.e. -;; -;; (set (reg:TI 32) -;; (const_int 0x8000000000000000)) -;; -;; Otherwise, the constant would be splatted into the 2 64-bit positions in the -;; vector register, and not loaded with the upper 64-bits 0, and the constant -;; in the lower 64-bits. - -(define_predicate "easy_vector_constant_64bit_element" - (match_code "const_vector,vec_duplicate") -{ - /* Can we do the XXSPLTIDP instruction? */ - if (!TARGET_XXSPLTIDP || !TARGET_PREFIXED || !TARGET_VSX) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (mode != V2DFmode && mode != V2DImode) - return false; - - if (CONST_VECTOR_P (op)) - { - if (!CONST_VECTOR_DUPLICATE_P (op)) - return false; - - op = CONST_VECTOR_ELT (op, 0); - } - - else if (GET_CODE (op) == VEC_DUPLICATE) - op = XEXP (op, 0); - - else - return false; - - return easy_fp_constant_64bit_scalar (op, GET_MODE_INNER (mode)); -}) - -;; Return 1 if the operand is a constant that can be loaded with the XXSPLTIW -;; instruction that loads up a 32-bit immediate and splats it into the vector. - -(define_predicate "easy_vector_constant_splat_word" - (match_code "const_vector") -{ - HOST_WIDE_INT value; - - if (!TARGET_PREFIXED || !TARGET_VSX || !TARGET_XXSPLTIW) - return false; - - rtx element0 = CONST_VECTOR_ELT (op, 0); - - switch (mode) - { - /* V4SImode constant vectors that have the same element are can be used - with XXSPLTIW. */ - case V4SImode: - if (!CONST_VECTOR_DUPLICATE_P (op)) - return false; - - /* Don't return true if we can use the shorter vspltisw instruction. */ - value = INTVAL (element0); - return (!EASY_VECTOR_15 (value)); - - /* V4SFmode constant vectors that have the same element are - can be used with XXSPLTIW. */ - case V4SFmode: - if (!CONST_VECTOR_DUPLICATE_P (op)) - return false; - - /* Don't return true for 0.0f, since that can be created with - xxspltib or xxlxor. */ - return (element0 != CONST0_RTX (SFmode)); - - /* V8Hmode constant vectors that have the same element are can be used - with XXSPLTIW. */ - case V8HImode: - if (CONST_VECTOR_DUPLICATE_P (op)) - { - /* Don't return true if we can use the shorter vspltish instruction. */ - value = INTVAL (element0); - if (EASY_VECTOR_15 (value)) - return false; - - return true; - } - - else - { - /* Check if all even elements are the same and all odd elements are - the same. */ - rtx element1 = CONST_VECTOR_ELT (op, 1); - - if (!CONST_INT_P (element1)) - return false; - - for (size_t i = 2; i < GET_MODE_NUNITS (V8HImode); i += 2) - if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i)) - || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1))) - return false; - - return true; - } - - /* V16QI constant vectors that have the first four elements identical to - the next set of 4 elements, and so forth can generate XXSPLTIW. */ - case V16QImode: - { - /* If we can use XXSPLTIB, don't generate XXSPLTIW. */ - if (xxspltib_constant_nosplit (op, mode)) - return false; - - rtx element1 = CONST_VECTOR_ELT (op, 1); - rtx element2 = CONST_VECTOR_ELT (op, 2); - rtx element3 = CONST_VECTOR_ELT (op, 3); - - if (!CONST_INT_P (element0) || !CONST_INT_P (element1) - || !CONST_INT_P (element2) || !CONST_INT_P (element3)) - return false; - - for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4) - if (!rtx_equal_p (element0, CONST_VECTOR_ELT (op, i)) - || !rtx_equal_p (element1, CONST_VECTOR_ELT (op, i + 1)) - || !rtx_equal_p (element2, CONST_VECTOR_ELT (op, i + 2)) - || !rtx_equal_p (element3, CONST_VECTOR_ELT (op, i + 3))) - return false; - - return true; - } - - default: - break; - } - - return false; -}) - ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. @@ -880,79 +640,6 @@ return num_insns == 1; }) -;; Return 1 if the operand is an IEEE 128-bit special constant that can be -;; loaded with the LXVKQ instruction. -(define_predicate "easy_fp_constant_ieee128" - (match_code "const_double") -{ - if (!TARGET_LXVKQ || !TARGET_POWER10 || !TARGET_VSX || !TARGET_FLOAT128_HW) - return false; - - if (mode == VOIDmode) - mode = GET_MODE (op); - - if (!FLOAT128_IEEE_P (mode)) - return false; - - if (!CONST_DOUBLE_P (op)) - return false; - - /* Special values (+/-infinity, -0.0. */ - const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op); - if (real_isinf (rv) || real_isnegzero (rv)) - return true; - - /* Only recognize the normal NaN. Do not recognize NaNs with the negative - sign, signaling NaNs, or NaNs that have non-zero mantissa. */ - if (real_isnan (rv)) - { - long w[4]; - - real_to_target (&w[0], rv, mode); - return (BYTES_BIG_ENDIAN - ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0 && w[3] == 0) - : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0 && w[0] == 0)); - } - - if (real_issignaling_nan (rv)) - return false; - - /* All of the values generated can be expressed as SFmode values, if it - doesn't fit in SFmode, exit. */ - if (!exact_real_truncate (SFmode, rv)) - return false; - - /* The other values are all integers 1..7, and -1..-7. */ - if (!real_isinteger (rv, mode)) - return false; - - HOST_WIDE_INT value = real_to_integer (rv); - switch (value) - { - default: - break; - - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - case -1: - case -2: - case -3: - case -4: - case -5: - case -6: - case -7: - return true; - } - - /* We can't load the value with LXVKQ. */ - return false; -}) - ;; Return 1 if the operand is a CONST_VECTOR and can be loaded into a ;; vector register without using memory. (define_predicate "easy_vector_constant" @@ -966,12 +653,6 @@ if (zero_constant (op, mode) || all_ones_constant (op, mode)) return true; - if (easy_vector_constant_64bit_element (op, mode)) - return true; - - if (easy_vector_constant_splat_word (op, mode)) - return true; - if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 540c401e7ad..14f6b313105 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -32,9 +32,6 @@ extern void init_cumulative_args (CUMULATIVE_ARGS *, tree, rtx, int, int, int, extern int easy_altivec_constant (rtx, machine_mode); extern bool xxspltib_constant_p (rtx, machine_mode, int *, int *); -extern long xxspltidp_constant_immediate (rtx, machine_mode); -extern long xxspltiw_constant_immediate (rtx, machine_mode); -extern int lxvkq_constant_immediate (rtx, machine_mode); extern int vspltis_shifted (rtx); extern HOST_WIDE_INT const_vector_elt_as_int (rtx, unsigned int); extern bool macho_lo_sum_memory_operand (rtx, machine_mode); @@ -201,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode); extern bool prefixed_load_p (rtx_insn *); extern bool prefixed_store_p (rtx_insn *); extern bool prefixed_paddi_p (rtx_insn *); -extern bool prefixed_xxsplti_p (rtx_insn *); extern void rs6000_asm_output_opcode (FILE *); extern void output_pcrel_opt_reloc (rtx); extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int); diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 1172fb999fc..ad860728169 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op, else if (IN_RANGE (value, -1, 0)) *num_insns_ptr = 1; - /* If we can generate the constant with a single XXSPLTIW don't generate a - XXSPLTIB and a sign extend operation. */ - else if (easy_vector_constant_splat_word (op, mode)) - return false; - else *num_insns_ptr = 2; @@ -6951,226 +6946,6 @@ xxspltib_constant_p (rtx op, return true; } -/* Return the immediate value used in the XXSPLTIDP instruction. */ - -long -xxspltidp_constant_immediate (rtx op, machine_mode mode) -{ - long ret; - - /* Handle vectors. */ - if (CONST_VECTOR_P (op)) - { - op = CONST_VECTOR_ELT (op, 0); - mode = GET_MODE_INNER (mode); - } - - else if (GET_CODE (op) == VEC_DUPLICATE) - { - op = XEXP (op, 0); - mode = GET_MODE (op); - } - - gcc_assert (easy_fp_constant_64bit_scalar (op, mode)); - - /* Handle DImode/V2DImode by creating a DF value from it and then converting - the DFmode value to SFmode. */ - if (CONST_INT_P (op)) - { - HOST_WIDE_INT df_value = INTVAL (op); - long df_words[2]; - - df_words[0] = (df_value >> 32) & 0xffffffff; - df_words[1] = df_value & 0xffffffff; - - /* real_to_target takes input in target endian order. */ - if (!BYTES_BIG_ENDIAN) - std::swap (df_words[0], df_words[1]); - - REAL_VALUE_TYPE r; - real_from_target (&r, &df_words[0], DFmode); - real_to_target (&ret, &r, SFmode); - } - - /* For floating point constants, convert to SFmode. */ - else if (CONST_DOUBLE_P (op) && (mode == SFmode || mode == DFmode)) - { - const REAL_VALUE_TYPE *rv = CONST_DOUBLE_REAL_VALUE (op); - real_to_target (&ret, rv, SFmode); - } - - else - gcc_unreachable (); - - return ret; -} - -/* Return the immediate value used in the XXSPLTIW instruction. */ -long -xxspltiw_constant_immediate (rtx op, machine_mode mode) -{ - long ret; - - gcc_assert (easy_vector_constant_splat_word (op, mode)); - - switch (mode) - { - default: - gcc_unreachable (); - - /* V4SImode constant vectors that have the same element are can be used - with XXSPLTIW. */ - case E_V4SImode: - gcc_assert (CONST_VECTOR_DUPLICATE_P (op)); - ret = INTVAL (CONST_VECTOR_ELT (op, 0)); - break; - - /* V4SFmode constant vectors that have the same element are - can be used with XXSPLTIW. */ - case E_V4SFmode: - gcc_assert (CONST_VECTOR_DUPLICATE_P (op)); - ret = rs6000_const_f32_to_i32 (CONST_VECTOR_ELT (op, 0)); - break; - - /* V8HImode constant vectors with all of the even elements the same and - all of the odd elements the same can used XXSPLTIW. */ - case E_V8HImode: - { - if (!rtx_equal_p (CONST_VECTOR_ELT (op, 0), CONST_VECTOR_ELT (op, 2)) - || !rtx_equal_p (CONST_VECTOR_ELT (op, 1), CONST_VECTOR_ELT (op, 3))) - gcc_unreachable (); - - long value0 = INTVAL (CONST_VECTOR_ELT (op, 0)) & 0xffff; - long value1 = INTVAL (CONST_VECTOR_ELT (op, 1)) & 0xffff; - - if (!BYTES_BIG_ENDIAN) - std::swap (value0, value1); - - ret = (value0 << 16) | value1; - } - break; - - /* V16QI constant vectors that have the first four elements identical to - the next set of 4 elements, and so forth can generate XXSPLTIW. */ - case E_V16QImode: - { - rtx op0 = CONST_VECTOR_ELT (op, 0); - rtx op1 = CONST_VECTOR_ELT (op, 1); - rtx op2 = CONST_VECTOR_ELT (op, 2); - rtx op3 = CONST_VECTOR_ELT (op, 3); - - for (size_t i = 4; i < GET_MODE_NUNITS (V16QImode); i += 4) - if (!rtx_equal_p (op0, CONST_VECTOR_ELT (op, i)) - || !rtx_equal_p (op1, CONST_VECTOR_ELT (op, i + 1)) - || !rtx_equal_p (op2, CONST_VECTOR_ELT (op, i + 2)) - || !rtx_equal_p (op3, CONST_VECTOR_ELT (op, i + 3))) - gcc_unreachable (); - - long value0 = INTVAL (op0) & 0xff; - long value1 = INTVAL (op1) & 0xff; - long value2 = INTVAL (op2) & 0xff; - long value3 = INTVAL (op3) & 0xff; - - ret = ((BYTES_BIG_ENDIAN) - ? ((value0 << 24) | (value1 << 16) | (value2 << 8) | value3) - : ((value3 << 24) | (value2 << 16) | (value1 << 8) | value0)); - } - break; - } - - return ret; -} - -/* Return the constant that will go in the LXVKQ instruction. */ - -/* LXVKQ immediates. */ -enum { - LXVKQ_ONE = 1, - LXVKQ_TWO = 2, - LXVKQ_THREE = 3, - LXVKQ_FOUR = 4, - LXVKQ_FIVE = 5, - LXVKQ_SIX = 6, - LXVKQ_SEVEN = 7, - LXVKQ_INF = 8, - LXVKQ_NAN = 9, - LXVKQ_NEG_ZERO = 16, - LXVKQ_NEG_ONE = 17, - LXVKQ_NEG_TWO = 18, - LXVKQ_NEG_THREE = 19, - LXVKQ_NEG_FOUR = 20, - LXVKQ_NEG_FIVE = 21, - LXVKQ_NEG_SIX = 22, - LXVKQ_NEG_SEVEN = 23, - LXVKQ_NEG_INF = 24 -}; - -int -lxvkq_constant_immediate (rtx op, machine_mode mode) -{ - int ret = -1; - gcc_assert (easy_fp_constant_ieee128 (op, mode)); - - const struct real_value *rv = CONST_DOUBLE_REAL_VALUE (op); - - gcc_assert (!real_issignaling_nan (rv)); - - /* Special values (infinity, nan, -0.0. */ - if (real_isinf (rv)) - ret = real_isneg (rv) ? LXVKQ_NEG_INF : LXVKQ_INF; - - /* Only recognize the normal NaN. Do not recognize NaNs with the negative - sign, signaling NaNs, or NaNs that have non-zero mantissa. */ - else if (real_isnan (rv)) - { - long w[4]; - - real_to_target (&w[0], rv, mode); - gcc_assert (BYTES_BIG_ENDIAN - ? (w[0] == 0x7fff8000 && w[1] == 0 && w[2] == 0 - && w[3] == 0) - : (w[3] == 0x7fff8000 && w[2] == 0 && w[1] == 0 - && w[0] == 0)); - - ret = LXVKQ_NAN; - } - - else if (real_isnegzero (rv)) - ret = LXVKQ_NEG_ZERO; - - else - { - HOST_WIDE_INT value = real_to_integer (rv); - switch (value) - { - default: - gcc_unreachable (); - - case 1: - case 2: - case 3: - case 4: - case 5: - case 6: - case 7: - ret = LXVKQ_ONE + (value - 1); - break; - - case -1: - case -2: - case -3: - case -4: - case -5: - case -6: - case -7: - ret = LXVKQ_NEG_ONE + (-value - 1); - break; - } - } - - return ret; -} - const char * output_vec_const_move (rtx *operands) { @@ -7215,25 +6990,6 @@ output_vec_const_move (rtx *operands) gcc_unreachable (); } - if (easy_fp_constant_64bit_scalar (vec, mode) - || easy_vector_constant_64bit_element (vec, mode)) - { - operands[2] = GEN_INT (xxspltidp_constant_immediate (vec, mode)); - return "xxspltidp %x0,%2"; - } - - if (easy_vector_constant_splat_word (vec, mode)) - { - operands[2] = GEN_INT (xxspltiw_constant_immediate (vec, mode)); - return "xxspltiw %x0,%2"; - } - - if (easy_fp_constant_ieee128 (vec, mode)) - { - operands[2] = GEN_INT (lxvkq_constant_immediate (vec, mode)); - return "lxvkq %x0,%2"; - } - if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -14076,12 +13832,6 @@ rs6000_output_move_128bit (rtx operands[]) } /* Constants. */ - else if (dest_vsx_p && easy_fp_constant_ieee128 (src, mode)) - { - operands[2] = GEN_INT (lxvkq_constant_immediate (src, mode)); - return "lxvkq %x0,%2"; - } - else if (dest_regno >= 0 && (CONST_INT_P (src) || CONST_WIDE_INT_P (src) @@ -26974,47 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn) return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL); } -/* Whether a permute type instruction is a prefixed XXSPLTI* instruction. - This is called from the prefixed attribute processing. */ - -bool -prefixed_xxsplti_p (rtx_insn *insn) -{ - rtx set = single_set (insn); - if (!set) - return false; - - rtx dest = SET_DEST (set); - rtx src = SET_SRC (set); - machine_mode mode = GET_MODE (dest); - - if (!REG_P (dest) && !SUBREG_P (dest)) - return false; - - switch (mode) - { - case E_DImode: - case E_DFmode: - case E_SFmode: - return easy_fp_constant_64bit_scalar (src, mode); - - case E_V2DImode: - case E_V2DFmode: - return easy_vector_constant_64bit_element (src, mode); - - case E_V16QImode: - case E_V8HImode: - case E_V4SImode: - case E_V4SFmode: - return easy_vector_constant_splat_word (src, mode); - - default: - break; - } - - return false; -} - /* Whether the next instruction needs a 'p' prefix issued before the instruction is printed out. */ static bool prepend_p_to_next_insn; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 8afc4b2756d..6bec2bddbde 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -314,11 +314,6 @@ (eq_attr "type" "integer,add") (if_then_else (match_test "prefixed_paddi_p (insn)") - (const_string "yes") - (const_string "no")) - - (eq_attr "type" "vecperm") - (if_then_else (match_test "prefixed_xxsplti_p (insn)") (const_string "yes") (const_string "no"))] @@ -7764,17 +7759,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT MF NOP XXSPLTIDP +;; MR MT MF NOP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h, wa") + !r, *c*l, !r, *h") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0, eF"))] + r, r, *h, 0"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7796,16 +7791,15 @@ mr %0,%1 mt%0 %1 mf%1 %0 - nop - #" + nop" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *, vecperm") + *, mtjmpr, mfjmpr, *") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *, p10")]) + *, *, *, *")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -8065,18 +8059,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR XXSPLTIDP +;; LWZ STW MR (define_insn "*mov_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, - Y, r, !r, wa") + Y, r, !r") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , - r, Y, r, eF"))] + r, Y, r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8093,21 +8087,20 @@ # # # - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two, vecperm") + store, load, two") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8, *") + 8, 8, 8") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *, p10")]) + *, *, *")]) ;; STW LWZ MR G-const H-const F-const @@ -8134,19 +8127,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFVSRD MTVSRD XXSPLTIDP +;; NOP MFVSRD MTVSRD (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, YZ, r, !r, *c*l, !r, - *h, r, , wa") + *h, r, ") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, YZ, r, r, *h, - 0, , r, eF"))] + 0, , r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8168,19 +8161,18 @@ mf%1 %0 nop mfvsrd %0,%x1 - mtvsrd %x0,%1 - #" + mtvsrd %x0,%1" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr, vecperm") + *, mfvsr, mtvsr") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, *, *, *, *, *, - *, p8v, p8v, p10")]) + *, p8v, p8v")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special @@ -9228,7 +9220,6 @@ ;; a gpr into a fpr instead of reloading an invalid 'Y' address ;; GPR store GPR load GPR move FPR store FPR load FPR move -;; XXSPLTIDP ;; GPR const AVX store AVX store AVX load AVX load VSX move ;; P9 0 P9 -1 AVX 0/-1 VSX 0 VSX -1 P9 const ;; AVX const @@ -9236,13 +9227,11 @@ (define_insn "*movdi_internal32" [(set (match_operand:DI 0 "nonimmediate_operand" "=Y, r, r, m, ^d, ^d, - ^wa, r, wY, Z, ^v, $v, ^wa, wa, wa, v, wa, *i, v, v") (match_operand:DI 1 "input_operand" "r, Y, r, ^d, m, ^d, - eF, IJKnF, ^v, $v, wY, Z, ^wa, Oj, wM, OjwM, Oj, wM, wS, wB"))] @@ -9257,7 +9246,6 @@ lfd%U1%X1 %0,%1 fmr %0,%1 # - # stxsd %1,%0 stxsdx %x1,%y0 lxsd %0,%1 @@ -9272,20 +9260,17 @@ #" [(set_attr "type" "store, load, *, fpstore, fpload, fpsimple, - vecperm, *, fpstore, fpstore, fpload, fpload, veclogical, vecsimple, vecsimple, vecsimple, veclogical,veclogical,vecsimple, vecsimple") (set_attr "size" "64") (set_attr "length" "8, 8, 8, *, *, *, - *, 16, *, *, *, *, *, *, *, *, *, *, 8, *") (set_attr "isa" "*, *, *, *, *, *, - p10, *, p9v, p7v, p9v, p7v, *, p9v, p9v, p7v, *, *, p7v, p7v")]) @@ -9321,7 +9306,6 @@ }) ;; GPR store GPR load GPR move -;; XXSPLTIDP ;; GPR li GPR lis GPR pli GPR # ;; FPR store FPR load FPR move ;; AVX store AVX store AVX load AVX load VSX move @@ -9332,7 +9316,6 @@ (define_insn "*movdi_internal64" [(set (match_operand:DI 0 "nonimmediate_operand" "=YZ, r, r, - ^wa, r, r, r, r, m, ^d, ^d, wY, Z, $v, $v, ^wa, @@ -9342,7 +9325,6 @@ ?r, ?wa") (match_operand:DI 1 "input_operand" "r, YZ, r, - eF, I, L, eI, nF, ^d, m, ^d, ^v, $v, wY, Z, ^wa, @@ -9357,7 +9339,6 @@ std%U0%X0 %1,%0 ld%U1%X1 %0,%1 mr %0,%1 - # li %0,%1 lis %0,%v1 li %0,%1 @@ -9384,7 +9365,6 @@ mtvsrd %x0,%1" [(set_attr "type" "store, load, *, - vecperm, *, *, *, *, fpstore, fpload, fpsimple, fpstore, fpstore, fpload, fpload, veclogical, @@ -9395,7 +9375,6 @@ (set_attr "size" "64") (set_attr "length" "*, *, *, - *, *, *, *, 20, *, *, *, *, *, *, *, *, @@ -9405,7 +9384,6 @@ *, *") (set_attr "isa" "*, *, *, - p10, *, *, p10, *, *, *, *, p9v, p7v, p9v, p7v, *, diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index a53aad72547..9d7878f144a 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -640,19 +640,6 @@ mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. -mxxspltidp -Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save -Generate (do not generate) XXSPLTIDP instructions. - -;; Do not enable at this time. -mxxspltiw -Target Undocumented Var(TARGET_XXSPLTIW) Init(0) Save -Generate (do not generate) XXSPLTIW instructions. - -mlxvkq -Target Undocumented Var(TARGET_LXVKQ) Init(1) Save -Generate (do not generate) LXVKQ instructions. - -param=rs6000-density-pct-threshold= Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param When costing for loop vectorization, we probably need to penalize the loop body diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 712e5df0c02..bf033e31c1c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1191,19 +1191,16 @@ ;; instruction). But generate XXLXOR/XXLORC if it will avoid a register move. ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) -;; XXSPLTIDP XXSPLTIW LXVKQ ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, - wa, wa, wa, ?&r, ??r, ??Y, , wa, v, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, - eV, eW, eQ, wQ, Y, r, r, wE, jwM, ?jwM, W, , v, wZ"))] @@ -1215,44 +1212,36 @@ } [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, - vecperm, vecperm, vecperm, store, load, store, *, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") (set_attr "num_insns" "*, *, *, 2, *, 2, - *, *, *, 2, 2, 2, 2, *, *, *, 5, 2, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, - *, *, *, 2, 2, 2, 2, *, *, *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, - *, *, *, 8, 8, 8, 8, *, *, *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, - p10, p10, p10, *, *, *, *, p9v, *, , *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move -;; XXSPLTIDP XXSPLTIW LXVKQ ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const ;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , - wa, wa, wa, wa, v, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, - eV, eW, eQ, wE, jwM, ?jwM, W, , v, wZ"))] @@ -1264,17 +1253,14 @@ } [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, - vecperm, vecperm, vecperm, vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, - *, *, *, *, *, *, 20, 16, *, *") (set_attr "isa" ", , , *, *, *, - p10, p10, p10, p9v, *, , *, *, *, *")]) @@ -6463,53 +6449,15 @@ DONE; }) -(define_mode_iterator XXSPLTIDP_S [DI SF DF]) -(define_mode_iterator XXSPLTIDP_V [V2DF V2DI]) -(define_mode_iterator XXSPLTIDP [DI SF DF V2DF V2DI]) - -(define_insn "xxspltidp__inst" - [(set (match_operand:XXSPLTIDP 0 "register_operand" "=wa") - (unspec:XXSPLTIDP [(match_operand:SI 1 "c32bit_cint_operand" "n")] - UNSPEC_XXSPLTIDP))] +(define_insn "xxspltidp_v2df_inst" + [(set (match_operand:V2DF 0 "register_operand" "=wa") + (unspec:V2DF [(match_operand:SI 1 "c32bit_cint_operand" "n")] + UNSPEC_XXSPLTIDP))] "TARGET_POWER10" "xxspltidp %x0,%1" [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) -;; Generate the XXSPLTIDP instruction to support SFmode, DFmode, and DImode -;; scalar constants and V2DF and V2DI vector constants where both elements are -;; the same. The constant has to be expressible as a SFmode constant that is -;; not a SFmode denormal value. -(define_insn_and_split "*xxspltidp__internal" - [(set (match_operand:XXSPLTIDP_S 0 "vsx_register_operand" "=wa") - (match_operand:XXSPLTIDP_S 1 "easy_fp_constant_64bit_scalar" "eF"))] - "TARGET_POWER10" - "#" - "&& 1" - [(set (match_dup 0) - (unspec:XXSPLTIDP_S [(match_dup 2)] UNSPEC_XXSPLTIDP))] -{ - long immediate = xxspltidp_constant_immediate (operands[1], mode); - operands[2] = GEN_INT (immediate); -} - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - -(define_insn_and_split "*xxspltidp__internal" - [(set (match_operand:XXSPLTIDP_V 0 "vsx_register_operand" "=wa") - (match_operand:XXSPLTIDP_V 1 "easy_vector_constant_64bit_element" "eV"))] - "TARGET_POWER10" - "#" - "&& 1" - [(set (match_dup 0) - (unspec:XXSPLTIDP_V [(match_dup 2)] UNSPEC_XXSPLTIDP))] -{ - long immediate = xxspltidp_constant_immediate (operands[1], mode); - operands[2] = GEN_INT (immediate); -} - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - ;; XXSPLTI32DX built-in function support (define_expand "xxsplti32dx_v4si" [(set (match_operand:V4SI 0 "register_operand" "=wa") diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 4ad0e745c94..2b41cb7fb7b 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3333,21 +3333,9 @@ The integer constant zero. A constant whose negation is a signed 16-bit constant. @end ifset -@item eF -A 64-bit scalar constant that can be loaded with the XXSPLTIDP instruction. - @item eI A signed 34-bit integer constant if prefixed instructions are supported. -@item eQ -An IEEE 128-bit constant that can be loaded with the LXVKQ instruction. - -@item eV -A 128-bit vector constant that can be loaded with the XXSPLTIDP instruction. - -@item eW -A vector constant that can be loaded with the XXSPLTIW instruction. - @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c deleted file mode 100644 index 23ee7e85d84..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c +++ /dev/null @@ -1,144 +0,0 @@ -/* { dg-require-effective-target ppc_float128_hw } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */ - -/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit - constants. */ - -_Float128 -return_0 (void) -{ - return 0.0f128; /* XXSPLTIB 34,0. */ -} - -_Float128 -return_1 (void) -{ - return 1.0f128; /* LXVKQ 34,1. */ -} - -_Float128 -return_2 (void) -{ - return 2.0f128; /* LXVKQ 34,2. */ -} - -_Float128 -return_3 (void) -{ - return 3.0f128; /* LXVKQ 34,3. */ -} - -_Float128 -return_4 (void) -{ - return 4.0f128; /* LXVKQ 34,4. */ -} - -_Float128 -return_5 (void) -{ - return 5.0f128; /* LXVKQ 34,5. */ -} - -_Float128 -return_6 (void) -{ - return 6.0f128; /* LXVKQ 34,6. */ -} - -_Float128 -return_7 (void) -{ - return 7.0f128; /* LXVKQ 34,7. */ -} - -_Float128 -return_m0 (void) -{ - return -0.0f128; /* LXVKQ 34,16. */ -} - -_Float128 -return_m1 (void) -{ - return -1.0f128; /* LXVKQ 34,17. */ -} - -_Float128 -return_m2 (void) -{ - return -2.0f128; /* LXVKQ 34,18. */ -} - -_Float128 -return_m3 (void) -{ - return -3.0f128; /* LXVKQ 34,19. */ -} - -_Float128 -return_m4 (void) -{ - return -4.0f128; /* LXVKQ 34,20. */ -} - -_Float128 -return_m5 (void) -{ - return -5.0f128; /* LXVKQ 34,21. */ -} - -_Float128 -return_m6 (void) -{ - return -6.0f128; /* LXVKQ 34,22. */ -} - -_Float128 -return_m7 (void) -{ - return -7.0f128; /* LXVKQ 34,23. */ -} - -_Float128 -return_inf (void) -{ - return __builtin_inff128 (); /* LXVKQ 34,8. */ -} - -_Float128 -return_minf (void) -{ - return - __builtin_inff128 (); /* LXVKQ 34,24. */ -} - -_Float128 -return_nan (void) -{ - return __builtin_nanf128 (""); /* LXVKQ 34,9. */ -} - -/* Note, the following NaNs should not generate a LXVKQ instruction. */ -_Float128 -return_mnan (void) -{ - return - __builtin_nanf128 (""); /* PLXV 34,... */ -} - -_Float128 -return_nan2 (void) -{ - return __builtin_nanf128 ("1"); /* PLXV 34,... */ -} - -_Float128 -return_nans (void) -{ - return __builtin_nansf128 (""); /* PLXV 34,... */ -} - -/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */ -/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ - diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c deleted file mode 100644 index 2707d86e6fd..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V16HI vector constants where the - first 4 elements are the same as the next 4 elements, etc. */ - -vector unsigned char -v16qi_const_1 (void) -{ - return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */ -} - -vector unsigned char -v16qi_const_2 (void) -{ - return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4, - 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c deleted file mode 100644 index 05d4ee3f5cb..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c +++ /dev/null @@ -1,67 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V4SF vector constants. */ - -vector float -v4sf_const_1 (void) -{ - return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_nan (void) -{ - return (vector float) { __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf ("") }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_inf (void) -{ - return (vector float) { __builtin_inff (), - __builtin_inff (), - __builtin_inff (), - __builtin_inff () }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_m0 (void) -{ - return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */ -} - -vector float -v4sf_splats_1 (void) -{ - return vec_splats (1.0f); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_nan (void) -{ - return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_inf (void) -{ - return vec_splats (__builtin_inff ()); /* XXSPLTIW. */ -} - -vector float -v8hi_splats_m0 (void) -{ - return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */ -/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c deleted file mode 100644 index da909e948b2..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure - the power9 support (XXSPLTIB/VEXTSB2W) is not done. */ - -vector int -v4si_const_1 (void) -{ - return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */ -} - -vector int -v4si_const_126 (void) -{ - return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector int -v4si_const_1023 (void) -{ - return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector int -v4si_splats_1 (void) -{ - return vec_splats (1); /* VSLTPISW. */ -} - -vector int -v4si_splats_126 (void) -{ - return vec_splats (126); /* XXSPLTIW. */ -} - -vector int -v8hi_splats_1023 (void) -{ - return vec_splats (1023); /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c deleted file mode 100644 index 290e05d4a64..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c +++ /dev/null @@ -1,62 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include - -/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure - the power9 support (XXSPLTIB/VUPKLSB) is not done. */ - -vector short -v8hi_const_1 (void) -{ - return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */ -} - -vector short -v8hi_const_126 (void) -{ - return (vector short) { 126, 126, 126, 126, - 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector short -v8hi_const_1023 (void) -{ - return (vector short) { 1023, 1023, 1023, 1023, - 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1 (void) -{ - return vec_splats ((short)1); /* VSLTPISH. */ -} - -vector short -v8hi_splats_126 (void) -{ - return vec_splats ((short)126); /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1023 (void) -{ - return vec_splats ((short)1023); /* XXSPLTIW. */ -} - -/* Test that we can optimiza V8HI where all of the even elements are the same - and all of the odd elements are the same. */ -vector short -v8hi_const_1023_1000 (void) -{ - return (vector short) { 1023, 1000, 1023, 1000, - 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */ -/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */