From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1461) id BB0FE385802A; Thu, 7 Oct 2021 10:32:12 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org BB0FE385802A MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Andrew Stubbs To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-4222] amdgcn: Fix assembler version incompatibility X-Act-Checkin: gcc X-Git-Author: Andrew Stubbs X-Git-Refname: refs/heads/master X-Git-Oldrev: 205dafb6edeca08419f4a5976be79bf7c86fd9a1 X-Git-Newrev: 81c362c7c2bccd72d798bf7ea6c74d4b1cc3931f Message-Id: <20211007103212.BB0FE385802A@sourceware.org> Date: Thu, 7 Oct 2021 10:32:12 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 07 Oct 2021 10:32:12 -0000 https://gcc.gnu.org/g:81c362c7c2bccd72d798bf7ea6c74d4b1cc3931f commit r12-4222-g81c362c7c2bccd72d798bf7ea6c74d4b1cc3931f Author: Andrew Stubbs Date: Thu Sep 30 17:50:33 2021 +0100 amdgcn: Fix assembler version incompatibility This is another case of the global_load instruction format changing in LLVM (because they fixed a bug). The configure test is already in place to detect what is needed. gcc/ChangeLog: * config/gcn/gcn-valu.md (gather_insn_2offsets): Apply HAVE_GCN_ASM_GLOBAL_LOAD_FIXED. (scatter_insn_2offsets): Likewise. Diff: --- gcc/config/gcn/gcn-valu.md | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/gcc/config/gcn/gcn-valu.md b/gcc/config/gcn/gcn-valu.md index 84ff67508b9..01fdce64d42 100644 --- a/gcc/config/gcn/gcn-valu.md +++ b/gcc/config/gcn/gcn-valu.md @@ -827,8 +827,12 @@ /* Work around assembler bug in which a 64-bit register is expected, but a 32-bit value would be correct. */ int reg = REGNO (operands[2]) - FIRST_VGPR_REG; - sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" - "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); + if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED) + sprintf (buf, "global_load%%o0\t%%0, v%d, %%1 offset:%%3%s\;" + "s_waitcnt\tvmcnt(0)", reg, glc); + else + sprintf (buf, "global_load%%o0\t%%0, v[%d:%d], %%1 offset:%%3%s\;" + "s_waitcnt\tvmcnt(0)", reg, reg + 1, glc); } else gcc_unreachable (); @@ -958,8 +962,12 @@ /* Work around assembler bug in which a 64-bit register is expected, but a 32-bit value would be correct. */ int reg = REGNO (operands[1]) - FIRST_VGPR_REG; - sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s", - reg, reg + 1, glc); + if (HAVE_GCN_ASM_GLOBAL_LOAD_FIXED) + sprintf (buf, "global_store%%s3\tv%d, %%3, %%0 offset:%%2%s", + reg, glc); + else + sprintf (buf, "global_store%%s3\tv[%d:%d], %%3, %%0 offset:%%2%s", + reg, reg + 1, glc); } else gcc_unreachable ();