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* [gcc(refs/users/meissner/heads/work071)] Add XXXSPLTIDP alternatives for 128-bit loads and stores.
@ 2021-10-13 21:16 Michael Meissner
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From: Michael Meissner @ 2021-10-13 21:16 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:c6ee64866c814d0cbde6eea247f2feb9eee4058d
commit c6ee64866c814d0cbde6eea247f2feb9eee4058d
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Wed Oct 13 17:15:45 2021 -0400
Add XXXSPLTIDP alternatives for 128-bit loads and stores.
2021-10-13 Michael Meissner <meissner@the-meissners.org>
gcc/
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add XXSPLTIDP
support.
(vsx_mov<mode>_32bit): Likewise.
Diff:
---
gcc/config/rs6000/vsx.md | 28 ++++++++++++++--------------
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 751a82e7710..7b2d2551c7b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,17 +1192,17 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
+;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) XXLSPLTIDP
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- ?wa, v, <??r>, wZ, v")
+ ?wa, v, <??r>, wZ, v, wa")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- ?jwM, W, <nW>, v, wZ"))]
+ ?jwM, W, <nW>, v, wZ, eD"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1213,37 +1213,37 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecsimple, *, *, vecstore, vecload")
+ vecsimple, *, *, vecstore, vecload, vecperm")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, 5, 2, *, *")
+ *, 5, 2, *, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *, *, *, *")
+ *, *, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, 20, 8, *, *")
+ *, 20, 8, *, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- <VSisa>, *, *, *, *")])
+ <VSisa>, *, *, *, *, p10")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const
-;; LVX (VMX) STVX (VMX)
+;; LVX (VMX) STVX (VMX) XXSPLTID LXVKQ
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa, v, <??r>,
- wZ, v")
+ wZ, v, wa")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM, W, <nW>,
- v, wZ"))]
+ v, wZ, eD"))]
"!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
&& (register_operand (operands[0], <MODE>mode)
@@ -1254,15 +1254,15 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple, *, *,
- vecstore, vecload")
+ vecstore, vecload, vecperm")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *, 20, 16,
- *, *")
+ *, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>, *, *,
- *, *")])
+ *, *, p10")])
;; Explicit load/store expanders for the builtin functions
(define_expand "vsx_load_<mode>"
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