From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 3CDCA3858D39; Thu, 14 Oct 2021 01:56:50 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 3CDCA3858D39 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work071)] Add LXVKQ support. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work071 X-Git-Oldrev: 005deaef00ea5999cc42f462a337436ec28ae7f7 X-Git-Newrev: 15d4edf91934579e414d52e5d6a1131af626645c Message-Id: <20211014015650.3CDCA3858D39@sourceware.org> Date: Thu, 14 Oct 2021 01:56:50 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 14 Oct 2021 01:56:50 -0000 https://gcc.gnu.org/g:15d4edf91934579e414d52e5d6a1131af626645c commit 15d4edf91934579e414d52e5d6a1131af626645c Author: Michael Meissner Date: Wed Oct 13 21:56:31 2021 -0400 Add LXVKQ support. This patch adds the basic support for generating the LXVKQ instruction. 2021-10-13 Michael Meissner gcc/ * config/rs6000/constraints.md (eQ): New constraint. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating the LXVKQ instruction. (easy_vector_constant_ieee128): New predicate. (easy_vector_constant): Add support for generating the LXVKQ instruction. * config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields for generating LXVKQ. * config/rs6000/rs6000.c (output_vec_const_move): Add support for generating LXVKQ. (vec_const_use_lxvkq): New function. * config/rs6000/rs6000.opt (-mlxvkq): New debug option. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for generating LXVKQ. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eQ constraint. gcc/testsuite/ * gcc.target/powerpc/float128-constant.c: New test. Diff: --- gcc/config/rs6000/constraints.md | 5 + gcc/config/rs6000/predicates.md | 25 ++++ gcc/config/rs6000/rs6000-protos.h | 3 + gcc/config/rs6000/rs6000.c | 57 ++++++++ gcc/config/rs6000/rs6000.opt | 4 + gcc/config/rs6000/vsx.md | 32 +++-- gcc/doc/md.texi | 3 + .../gcc.target/powerpc/float128-constant.c | 144 +++++++++++++++++++++ 8 files changed, 261 insertions(+), 12 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index d26c8940104..a15b659d9d7 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -218,6 +218,11 @@ "A signed 34-bit integer constant if prefixed instructions are supported." (match_operand 0 "cint34_operand")) +;; 128-bit IEEE 128-bit constant +(define_constraint "eQ" + "An IEEE 128-bit constant that can be loaded with the LXVKQ instruction." + (match_operand 0 "easy_vector_constant_ieee128")) + ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index ddad7ca3ae9..2c9c0a29845 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -609,6 +609,9 @@ { if (vec_const_use_xxspltidp (&vec_const)) return true; + + if (vec_const_use_lxvkq (&vec_const)) + return true; } /* Otherwise consider floating point constants hard, so that the @@ -639,6 +642,25 @@ return vec_const_use_xxspltidp (&vec_const); }) +;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded +;; via the LXVKQ instruction. + +(define_predicate "easy_vector_constant_ieee128" + (match_code "const_vector,vec_duplicate,const_int,const_double") +{ + rs6000_vec_const vec_const; + + /* Can we do the LXVKQ instruction? */ + if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX) + return false; + + /* Convert the vector constant to bytes. */ + if (!vec_const_to_bytes (op, mode, &vec_const)) + return false; + + return vec_const_use_lxvkq (&vec_const); +}) + ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. @@ -695,6 +717,9 @@ { if (vec_const_use_xxspltidp (&vec_const)) return true; + + if (vec_const_use_lxvkq (&vec_const)) + return true; } return easy_altivec_constant (op, mode); diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index da9502bcb33..388fe18e314 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -243,11 +243,14 @@ typedef struct { bool is_xxspltidp; /* Use XXSPLTIDP to load constant. */ machine_mode xxspltidp_mode; /* Mode to use for XXSPLTIDP. */ unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */ + bool is_lxvkq; /* LXVKQ can load the constant. */ + unsigned lxvkq_immediate; /* Immediate to use with LXVKQ. */ bool is_prefixed; /* Prefixed instruction used. */ } rs6000_vec_const; extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *); extern bool vec_const_use_xxspltidp (rs6000_vec_const *); +extern bool vec_const_use_lxvkq (rs6000_vec_const *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 05b2691d38a..2a038ea7dea 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6993,6 +6993,12 @@ output_vec_const_move (rtx *operands) rs6000_vec_const vec_const; if (vec_const_to_bytes (vec, mode, &vec_const)) { + if (vec_const_use_lxvkq (&vec_const)) + { + operands[2] = GEN_INT (vec_const.lxvkq_immediate); + return "lxvkq %x0,%2"; + } + if (vec_const_use_xxspltidp (&vec_const)) { operands[2] = GEN_INT (vec_const.xxspltidp_immediate); @@ -28786,6 +28792,57 @@ vec_const_use_xxspltidp (rs6000_vec_const *vec_const) return true; } +/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out + the fields used to generate the instruction. */ + +bool +vec_const_use_lxvkq (rs6000_vec_const *vec_const) +{ + unsigned immediate; + + if (!TARGET_LXVKQ || !TARGET_PREFIXED || !TARGET_VSX) + return false; + + /* Verify that all of the bottom 3 words in the constants loaded by the + LXVKQ instruction are zero. */ + for (size_t i = 1; i < VECTOR_CONST_32BIT; i++) + if (vec_const->words[i] != 0) + return false; + + /* See if we have a match. */ + switch (vec_const->words[0]) + { + case 0x3FFF0000U: immediate = 1; break; /* IEEE 128-bit +1.0. */ + case 0x40000000U: immediate = 2; break; /* IEEE 128-bit +2.0. */ + case 0x40008000U: immediate = 3; break; /* IEEE 128-bit +3.0. */ + case 0x40010000U: immediate = 4; break; /* IEEE 128-bit +4.0. */ + case 0x40014000U: immediate = 5; break; /* IEEE 128-bit +5.0. */ + case 0x40018000U: immediate = 6; break; /* IEEE 128-bit +6.0. */ + case 0x4001C000U: immediate = 7; break; /* IEEE 128-bit +7.0. */ + case 0x7FFF0000U: immediate = 8; break; /* IEEE 128-bit +Infinity. */ + case 0x7FFF8000U: immediate = 9; break; /* IEEE 128-bit quiet NaN. */ + case 0x80000000U: immediate = 16; break; /* IEEE 128-bit -0.0. */ + case 0xBFFF0000U: immediate = 17; break; /* IEEE 128-bit -1.0. */ + case 0xC0000000U: immediate = 18; break; /* IEEE 128-bit -2.0. */ + case 0xC0008000U: immediate = 19; break; /* IEEE 128-bit -3.0. */ + case 0xC0010000U: immediate = 20; break; /* IEEE 128-bit -4.0. */ + case 0xC0014000U: immediate = 21; break; /* IEEE 128-bit -5.0. */ + case 0xC0018000U: immediate = 22; break; /* IEEE 128-bit -6.0. */ + case 0xC001C000U: immediate = 23; break; /* IEEE 128-bit -7.0. */ + case 0xFFFF0000U: immediate = 24; break; /* IEEE 128-bit -Infinity. */ + + /* anything else cannot be loaded. */ + default: + return false; + } + + /* We can use the LXVKQ instruction. */ + vec_const->lxvkq_immediate = immediate; + vec_const->is_lxvkq = true; + vec_const->is_prefixed = false; + return true; +} + /* Convert a vector constant to an internal structure, breaking it out to bytes, half words, words, and double words. Return true if we have successfully broken it out. */ diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 1d7ce4cc94a..c9eb78952d6 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -644,6 +644,10 @@ mxxspltidp Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save Generate (do not generate) XXSPLTIDP instructions. +mlxvkq +Target Undocumented Var(TARGET_LXVKQ) Init(1) Save +Generate (do not generate) LXVKQ instructions. + -param=rs6000-density-pct-threshold= Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param When costing for loop vectorization, we probably need to penalize the loop body diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 7b2d2551c7b..eddbf395e77 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1193,16 +1193,19 @@ ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) XXLSPLTIDP +;; LXVKQ (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, - ?wa, v, , wZ, v, wa") + ?wa, v, , wZ, v, wa, + wa") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, - ?jwM, W, , v, wZ, eD"))] + ?jwM, W, , v, wZ, eD, + eQ"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) @@ -1213,23 +1216,28 @@ [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, store, load, store, *, vecsimple, vecsimple, - vecsimple, *, *, vecstore, vecload, vecperm") + vecsimple, *, *, vecstore, vecload, vecperm, + vecperm") (set_attr "num_insns" "*, *, *, 2, *, 2, 2, 2, 2, 2, *, *, - *, 5, 2, *, *, *") + *, 5, 2, *, *, *, + *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, 2, 2, 2, 2, *, *, - *, *, *, *, *, *") + *, *, *, *, *, *, + *") (set_attr "length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, - *, 20, 8, *, *, *") + *, 20, 8, *, *, *, + *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, - , *, *, *, *, p10")]) + , *, *, *, *, p10, + p10")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move ;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const @@ -1238,12 +1246,12 @@ [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , wa, v, ?wa, v, , - wZ, v, wa") + wZ, v, wa, wa") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, wE, jwM, ?jwM, W, , - v, wZ, eD"))] + v, wZ, eD, eQ"))] "!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) && (register_operand (operands[0], mode) @@ -1254,15 +1262,15 @@ [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, vecsimple, vecsimple, vecsimple, *, *, - vecstore, vecload, vecperm") + vecstore, vecload, vecperm, vecperm") (set_attr "length" "*, *, *, 16, 16, 16, *, *, *, 20, 16, - *, *, *") + *, *, *, *") (set_attr "isa" ", , , *, *, *, p9v, *, , *, *, - *, *, p10")]) + *, *, p10, p10")]) ;; Explicit load/store expanders for the builtin functions (define_expand "vsx_load_" diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index b9dfcaf0d44..501e0069ebb 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3339,6 +3339,9 @@ A constant that can be loaded with the XXSPLTIDP instruction. @item eI A signed 34-bit integer constant if prefixed instructions are supported. +@item eQ +A constant that can be loaded with the LXVKQ instruction. + @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c new file mode 100644 index 00000000000..23ee7e85d84 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-constant.c @@ -0,0 +1,144 @@ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -mlxvkq -O2" } */ + +/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit + constants. */ + +_Float128 +return_0 (void) +{ + return 0.0f128; /* XXSPLTIB 34,0. */ +} + +_Float128 +return_1 (void) +{ + return 1.0f128; /* LXVKQ 34,1. */ +} + +_Float128 +return_2 (void) +{ + return 2.0f128; /* LXVKQ 34,2. */ +} + +_Float128 +return_3 (void) +{ + return 3.0f128; /* LXVKQ 34,3. */ +} + +_Float128 +return_4 (void) +{ + return 4.0f128; /* LXVKQ 34,4. */ +} + +_Float128 +return_5 (void) +{ + return 5.0f128; /* LXVKQ 34,5. */ +} + +_Float128 +return_6 (void) +{ + return 6.0f128; /* LXVKQ 34,6. */ +} + +_Float128 +return_7 (void) +{ + return 7.0f128; /* LXVKQ 34,7. */ +} + +_Float128 +return_m0 (void) +{ + return -0.0f128; /* LXVKQ 34,16. */ +} + +_Float128 +return_m1 (void) +{ + return -1.0f128; /* LXVKQ 34,17. */ +} + +_Float128 +return_m2 (void) +{ + return -2.0f128; /* LXVKQ 34,18. */ +} + +_Float128 +return_m3 (void) +{ + return -3.0f128; /* LXVKQ 34,19. */ +} + +_Float128 +return_m4 (void) +{ + return -4.0f128; /* LXVKQ 34,20. */ +} + +_Float128 +return_m5 (void) +{ + return -5.0f128; /* LXVKQ 34,21. */ +} + +_Float128 +return_m6 (void) +{ + return -6.0f128; /* LXVKQ 34,22. */ +} + +_Float128 +return_m7 (void) +{ + return -7.0f128; /* LXVKQ 34,23. */ +} + +_Float128 +return_inf (void) +{ + return __builtin_inff128 (); /* LXVKQ 34,8. */ +} + +_Float128 +return_minf (void) +{ + return - __builtin_inff128 (); /* LXVKQ 34,24. */ +} + +_Float128 +return_nan (void) +{ + return __builtin_nanf128 (""); /* LXVKQ 34,9. */ +} + +/* Note, the following NaNs should not generate a LXVKQ instruction. */ +_Float128 +return_mnan (void) +{ + return - __builtin_nanf128 (""); /* PLXV 34,... */ +} + +_Float128 +return_nan2 (void) +{ + return __builtin_nanf128 ("1"); /* PLXV 34,... */ +} + +_Float128 +return_nans (void) +{ + return __builtin_nansf128 (""); /* PLXV 34,... */ +} + +/* { dg-final { scan-assembler-times {\mlxvkq\M} 18 } } */ +/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ +