[gcc(refs/users/meissner/heads/work071)] Update ChangeLog.meissner.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:dd58bdd9d1eb4f48486f6d8f027edeebfea3a0f8

commit dd58bdd9d1eb4f48486f6d8f027edeebfea3a0f8
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Oct 13 22:54:18 2021 -0400

    Update ChangeLog.meissner.
    
    gcc/
    2021-10-13  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.
    
    gcc/testsuite/
    2021-10-13  Michael Meissner  <meissner@linux.ibm.com>
    
            * ChangeLog.meissner: Update.

Diff:
---
 gcc/ChangeLog.meissner           | 40 ++++++++++++++++++++++++++++++++++++++++
 gcc/testsuite/ChangeLog.meissner |  5 +++++
 2 files changed, 45 insertions(+)

diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner
index cae42135473..34f1b47e887 100644
--- a/gcc/ChangeLog.meissner
+++ b/gcc/ChangeLog.meissner
@@ -1,3 +1,43 @@
+work071.patch006:
+2021-10-13  Michael Meissner  <meissner@the-meissners.org>
+
+	* config/rs6000/constraints.md (eQ): New constraint.
+	* config/rs6000/predicates.md (easy_fp_constant): Add support for
+	generating the LXVKQ instruction.
+	(easy_vector_constant_ieee128): New predicate.
+	(easy_vector_constant): Add support for generating the LXVKQ
+	instruction.
+	* config/rs6000/rs6000-protos.h (rs6000_vec_concat): Add fields
+	for generating LXVKQ.
+	* config/rs6000/rs6000.c (output_vec_const_move): Add support for
+	generating LXVKQ.
+	(vec_const_use_lxvkq): New function.
+	* config/rs6000/rs6000.opt (-mlxvkq): New debug option.
+	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
+	generating LXVKQ.
+	(vsx_mov<mode>_32bit): Likewise.
+	* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
+	eQ constraint.
+
+work071.patch005:
+2021-10-13  Michael Meissner  <meissner@the-meissners.org>
+
+	* config/rs6000/predicates.md (easy_fp_constant): Move to using
+	vec_const instead of calling easy_vector_constant_64bit_element.
+	(easy_vector_constant): Likewise.
+	* config/rs6000/rs6000.c (output_vec_const_move): Rework code
+	slightly to improve future patches.
+	(prefixed_xxsplti_p): Likewise.
+	(vec_const_to_bytes): SFmode as a scalar in registers uses the
+	DFmode format.
+
+work071.patch004:
+2021-10-13  Michael Meissner  <meissner@the-meissners.org>
+
+	* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add XXSPLTIDP
+	support.
+	(vsx_mov<mode>_32bit): Likewise.
+
 work071.patch003:
 2021-10-13  Michael Meissner  <meissner@the-meissners.org>
 
diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner
index 555a4888ef3..c6c864b07e7 100644
--- a/gcc/testsuite/ChangeLog.meissner
+++ b/gcc/testsuite/ChangeLog.meissner
@@ -1,3 +1,8 @@
+work071.patch006:
+2021-10-13  Michael Meissner  <meissner@the-meissners.org>
+
+	* gcc.target/powerpc/float128-constant.c: New test.
+
 work071.patch001:
 2021-10-12  Michael Meissner  <meissner@the-meissners.org>