public inbox for gcc-cvs@sourceware.org
help / color / mirror / Atom feed
From: Michael Meissner <meissner@gcc.gnu.org>
To: gcc-cvs@gcc.gnu.org
Subject: [gcc(refs/users/meissner/heads/work071)] Generate XXSPLTIW on power10.
Date: Thu, 14 Oct 2021 18:15:03 +0000 (GMT) [thread overview]
Message-ID: <20211014181503.F0C353858412@sourceware.org> (raw)
https://gcc.gnu.org/g:90e34b175735acc14d2ddaf5be4411ad418c559e
commit 90e34b175735acc14d2ddaf5be4411ad418c559e
Author: Michael Meissner <meissner@linux.ibm.com>
Date: Thu Oct 14 14:14:43 2021 -0400
Generate XXSPLTIW on power10.
This patch adds support to automatically generate the ISA 3.1 XXSPLTIW
instruction for V8HImode, V4SImode, and V4SFmode vectors. It does this by
adding support for vector constants that can be used, and adding a
VEC_DUPLICATE pattern to generate the actual XXSPLTIW instruction.
I rewrote the XXSPLTW built-in functions to use VEC_DUPLICATE instead of
UNSPEC.
This patch also updates the insn counts in the vec-splati-runnable.c test to
work with the new option to use XXSPLTIW to load up some vector constants.
I added 4 new tests to test loading up V16QI, V8HI, V4SI, and V4SF vector
constants.
2021-10-14 Michael Meissner <meissner@linux.ibm.com>
gcc/
* config/rs6000/constraints.md (eW): New constraint.
* config/rs6000/predicates.md (easy_fp_constant): Add support for
XXSPLTIW.
(easy_vector_constant_32bit_element): New predicate.
(easy_vector_constant): Add support for XXSPLTIW.
* config/rs6000/rs6000-protos.h (rs6000_vec_const): Add fields for
XXSPLTIW.
(vec_const_use_xxspltiw): New declaration.
* config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate
XXSPLTIW, don't do XXSPLTIB and sign extend.
(output_vec_const_move): Add support for XXSPLTIW.
(prefixed_xxsplti_p): Recognize XXSPLTIW instructions as
prefixed.
(vec_const_use_xxspltiw): New function.
* config/rs6000/rs6000.opt (-mxxspltiw): New debug switch.
* config/rs6000/vsx.md (vsx_mov<mode>_64bit): Add support for
constants loaded with XXSPLTIW.
(vsx_mov<mode>_32bit): Likewise.
* doc/md.texi (PowerPC and IBM RS6000 constraints): Document the
eW constraint.
gcc/testsuite/
* gcc.target/powerpc/vec-splat-constant-v16qi.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4sf.c: New test.
* gcc.target/powerpc/vec-splat-constant-v4si.c: New test.
* gcc.target/powerpc/vec-splat-constant-v8hi.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 5 +
gcc/config/rs6000/predicates.md | 22 ++++
gcc/config/rs6000/rs6000-protos.h | 2 +
gcc/config/rs6000/rs6000.c | 123 ++++++++++++++++++++-
gcc/config/rs6000/rs6000.opt | 4 +
gcc/config/rs6000/vsx.md | 28 ++---
.../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 +++++
.../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 +++++++++++
.../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 +++++++++
.../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 +++++++++++
10 files changed, 371 insertions(+), 20 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index a15b659d9d7..d2a1c088995 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -223,6 +223,11 @@
"An IEEE 128-bit constant that can be loaded with the LXVKQ instruction."
(match_operand 0 "easy_vector_constant_ieee128"))
+;; A scalar or vector constant that can be loaded with the XXSPLTIW instruction.
+(define_constraint "eW"
+ "A constant that can be loaded with the XXSPLTIW instruction."
+ (match_operand 0 "easy_vector_constant_32bit_element"))
+
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index de191fff08a..2a2bdbe463a 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -611,6 +611,9 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
+
+ if (vec_const_use_xxspltiw (&vec_const))
+ return true;
}
/* Otherwise consider floating point constants hard, so that the
@@ -638,6 +641,22 @@
&& vec_const_use_xxspltidp (&vec_const));
})
+;; Return 1 if the operand is a 32-bit vector constant that can be loaded via
+;; the XXSPLTIW instruction.
+
+(define_predicate "easy_vector_constant_32bit_element"
+ (match_code "const_vector,vec_duplicate,const_int,const_double")
+{
+ rs6000_vec_const vec_const;
+
+ /* Can we do the XXSPLTIW instruction? */
+ if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
+ return false;
+
+ return (vec_const_to_bytes (op, mode, &vec_const)
+ && vec_const_use_xxspltiw (&vec_const));
+})
+
;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded
;; via the LXVKQ instruction.
@@ -713,6 +732,9 @@
if (vec_const_use_xxspltidp (&vec_const))
return true;
+
+ if (vec_const_use_xxspltiw (&vec_const))
+ return true;
}
return easy_altivec_constant (op, mode);
diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h
index 43c0f96aab5..db0ad716968 100644
--- a/gcc/config/rs6000/rs6000-protos.h
+++ b/gcc/config/rs6000/rs6000-protos.h
@@ -240,11 +240,13 @@ typedef struct {
unsigned char bytes[VECTOR_CONST_BYTES];
machine_mode orig_mode; /* Original mode. */
unsigned int xxspltidp_immediate; /* Immediate value for XXSPLTIDP. */
+ unsigned int xxspltiw_immediate; /* Immediate value for XXSPLTIW. */
unsigned lxvkq_immediate; /* Immediate to use with LXVKQ. */
} rs6000_vec_const;
extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *);
extern bool vec_const_use_xxspltidp (rs6000_vec_const *);
+extern bool vec_const_use_xxspltiw (rs6000_vec_const *);
extern bool vec_const_use_lxvkq (rs6000_vec_const *);
#endif /* RTX_CODE */
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 359379348bb..1bd3f7c9c52 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -6925,12 +6925,17 @@ xxspltib_constant_p (rtx op,
else
return false;
- /* See if we could generate vspltisw/vspltish directly instead of xxspltib +
- sign extend. Special case 0/-1 to allow getting any VSX register instead
- of an Altivec register. */
- if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0)
- && EASY_VECTOR_15 (value))
- return false;
+ /* See if we could generate vspltisw/vspltish/xxspltiw directly instead of
+ xxspltib + sign extend. Special case 0/-1 to allow getting any VSX
+ register instead of an Altivec register. */
+ if ((mode == V4SImode || mode == V8HImode) && !IN_RANGE (value, -1, 0))
+ {
+ if (EASY_VECTOR_15 (value))
+ return false;
+
+ if (TARGET_XXSPLTIW && TARGET_PREFIXED && TARGET_VSX)
+ return false;
+ }
/* Return # of instructions and the constant byte for XXSPLTIB. */
if (mode == V16QImode)
@@ -7004,6 +7009,52 @@ output_vec_const_move (rtx *operands)
operands[2] = GEN_INT (vec_const.xxspltidp_immediate);
return "xxspltidp %x0,%2";
}
+
+ if (vec_const_use_xxspltiw (&vec_const))
+ {
+ HOST_WIDE_INT imm = vec_const.xxspltiw_immediate;
+
+ /* See if we can generate the shorter VSPLTISB, VSPLTISH, or
+ VSPLTISW instead of XXSPLTIW. */
+ if (dest_vmx_p)
+ {
+ HOST_WIDE_INT sign_imm
+ = ((imm & 0xffffffff) ^ 0x80000000) - 0x80000000;
+
+ if (EASY_VECTOR_15 (sign_imm))
+ {
+ operands[2] = GEN_INT (sign_imm);
+ return "vspltisw %0,%2";
+ }
+
+ if (vec_const.bytes[0] == vec_const.bytes[1]
+ && vec_const.bytes[0] == vec_const.bytes[2]
+ && vec_const.bytes[0] == vec_const.bytes[3])
+ {
+ HOST_WIDE_INT sign_imm8 = ((imm & 0xff) ^ 0x80) - 0x80;
+ if (EASY_VECTOR_15 (sign_imm8))
+ {
+ operands[2] = GEN_INT (sign_imm8);
+ return "vspltisb %0,%2";
+ }
+ }
+
+ if (vec_const.h_words[0] == vec_const.h_words[1])
+ {
+ HOST_WIDE_INT sign_imm16
+ = ((imm & 0xffff) ^ 0x8000) - 0x8000;
+
+ if (EASY_VECTOR_15 (sign_imm16))
+ {
+ operands[2] = GEN_INT (sign_imm16);
+ return "vspltish %0,%2";
+ }
+ }
+ }
+
+ operands[2] = GEN_INT (imm);
+ return "xxspltiw %x0,%2";
+ }
}
if (TARGET_P9_VECTOR
@@ -26770,6 +26821,9 @@ prefixed_xxsplti_p (rtx_insn *insn)
{
if (vec_const_use_xxspltidp (&vec_const))
return true;
+
+ if (vec_const_use_xxspltiw (&vec_const))
+ return true;
}
return false;
@@ -28793,6 +28847,63 @@ vec_const_use_xxspltidp (rs6000_vec_const *vec_const)
return true;
}
+/* Determine if a vector constant can be loaded with XXSPLTIW. If so,
+ fill out the fields used to generate the instruction. */
+
+bool
+vec_const_use_xxspltiw (rs6000_vec_const *vec_const)
+{
+ if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX)
+ return false;
+
+ /* Make sure that each of the 4 32-bit segments are the same. */
+ unsigned int value = vec_const->words[0];
+ if (value != vec_const->words[1]
+ || value != vec_const->words[2]
+ || value != vec_const->words[3])
+ return false;
+
+ /* Avoid values that are easy to create with other instructions (0.0 for
+ floating point, and values that can be loaded with VSPLTIW.. */
+ if (value == 0)
+ return false;
+
+ machine_mode mode = vec_const->orig_mode;
+ if (mode == VOIDmode)
+ mode = SImode;
+
+ if (!FLOAT_MODE_P (mode))
+ {
+ /* Can we use VSPLTISW to load the constant? */
+ int sign_value = ((value & 0xffffffff) ^ 0x80000000) - 0x80000000;
+ if (EASY_VECTOR_15 (sign_value))
+ return false;
+
+ /* Can we use VSPLTISB to load the constant? */
+ if (vec_const->bytes[0] == vec_const->bytes[1]
+ && vec_const->bytes[0] == vec_const->bytes[2]
+ && vec_const->bytes[0] == vec_const->bytes[3])
+ {
+ int sign_value8 = ((value & 0xff) ^ 0x80) - 0x80;
+ if (EASY_VECTOR_15 (sign_value8))
+ return false;
+ }
+
+ /* Can we use VSPLTISH to load the constant? */
+ if (vec_const->h_words[0] == vec_const->h_words[1])
+ {
+ int sign_value16 = ((value & 0xffff) ^ 0x8000) - 0x8000;
+ if (EASY_VECTOR_15 (sign_value16))
+ return false;
+ }
+ }
+
+ /* Record the immediate in the vec_const structure for XXSPLTIW. */
+ vec_const->xxspltiw_immediate = value;
+
+ return true;
+}
+
/* Determine if a vector constant can be loaded with LXVKQ. If so, fill out
the fields used to generate the instruction. */
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c9eb78952d6..015bf91b6d5 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -644,6 +644,10 @@ mxxspltidp
Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save
Generate (do not generate) XXSPLTIDP instructions.
+mxxspltiw
+Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save
+Generate (do not generate) XXSPLTIW instructions.
+
mlxvkq
Target Undocumented Var(TARGET_LXVKQ) Init(1) Save
Generate (do not generate) LXVKQ instructions.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index b36bbcd2b4e..0d0609b5d0b 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -1192,19 +1192,19 @@
;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR)
;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW
-;; XXLSPLTIDP LXVKQ
+;; XXLSPLTIDP LXVKQ XXSPLTIW
;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX)
(define_insn "vsx_mov<mode>_64bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, r, we, ?wQ,
?&r, ??r, ??Y, <??r>, wa, v,
- wa, wa,
+ wa, wa, wa,
?wa, v, <??r>, wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, we, r, r,
wQ, Y, r, r, wE, jwM,
- eD, eQ,
+ eD, eQ, eW,
?jwM, W, <nW>, v, wZ"))]
"TARGET_POWERPC64 && VECTOR_MEM_VSX_P (<MODE>mode)
@@ -1216,46 +1216,46 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, mtvsr, mfvsr, load,
store, load, store, *, vecsimple, vecsimple,
- vecperm, vecperm,
+ vecperm, vecperm, vecperm,
vecsimple, *, *, vecstore, vecload")
(set_attr "num_insns"
"*, *, *, 2, *, 2,
2, 2, 2, 2, *, *,
- *, *,
+ *, *, *,
*, 5, 2, *, *")
(set_attr "max_prefixed_insns"
"*, *, *, *, *, 2,
2, 2, 2, 2, *, *,
- *, *,
+ *, *, *,
*, *, *, *, *")
(set_attr "length"
"*, *, *, 8, *, 8,
8, 8, 8, 8, *, *,
- *, *,
+ *, *, *,
*, 20, 8, *, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
*, *, *, *, p9v, *,
- p10, p10,
+ p10, p10, p10,
<VSisa>, *, *, *, *")])
;; VSX store VSX load VSX move GPR load GPR store GPR move
;; XXSPLTIB VSPLTISW VSX 0/-1
-;; XXSPLTIDP LXVKQ
+;; XXSPLTIDP LXVKQ XXSPLTIW
;; VMX const GPR const
;; LVX (VMX) STVX (VMX)
(define_insn "*vsx_mov<mode>_32bit"
[(set (match_operand:VSX_M 0 "nonimmediate_operand"
"=ZwO, wa, wa, ??r, ??Y, <??r>,
wa, v, ?wa,
- wa, wa,
+ wa, wa, wa,
v, <??r>,
wZ, v")
(match_operand:VSX_M 1 "input_operand"
"wa, ZwO, wa, Y, r, r,
wE, jwM, ?jwM,
- eD, eQ,
+ eD, eQ, eW,
W, <nW>,
v, wZ"))]
@@ -1268,19 +1268,19 @@
[(set_attr "type"
"vecstore, vecload, vecsimple, load, store, *,
vecsimple, vecsimple, vecsimple,
- vecperm, vecperm,
+ vecperm, vecperm, vecperm,
*, *,
vecstore, vecload")
(set_attr "length"
"*, *, *, 16, 16, 16,
*, *, *,
- *, *,
+ *, *, *,
20, 16,
*, *")
(set_attr "isa"
"<VSisa>, <VSisa>, <VSisa>, *, *, *,
p9v, *, <VSisa>,
- p10, p10,
+ p10, p10, p10,
*, *,
*, *")])
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
new file mode 100644
index 00000000000..2707d86e6fd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c
@@ -0,0 +1,27 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
+
+#include <altivec.h>
+
+/* Test whether XXSPLTIW is generated for V16HI vector constants where the
+ first 4 elements are the same as the next 4 elements, etc. */
+
+vector unsigned char
+v16qi_const_1 (void)
+{
+ return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1,
+ 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */
+}
+
+vector unsigned char
+v16qi_const_2 (void)
+{
+ return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4,
+ 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */
+/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */
+/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
+/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
new file mode 100644
index 00000000000..05d4ee3f5cb
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c
@@ -0,0 +1,67 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
+
+#include <altivec.h>
+
+/* Test whether XXSPLTIW is generated for V4SF vector constants. */
+
+vector float
+v4sf_const_1 (void)
+{
+ return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */
+}
+
+vector float
+v4sf_const_nan (void)
+{
+ return (vector float) { __builtin_nanf (""),
+ __builtin_nanf (""),
+ __builtin_nanf (""),
+ __builtin_nanf ("") }; /* XXSPLTIW. */
+}
+
+vector float
+v4sf_const_inf (void)
+{
+ return (vector float) { __builtin_inff (),
+ __builtin_inff (),
+ __builtin_inff (),
+ __builtin_inff () }; /* XXSPLTIW. */
+}
+
+vector float
+v4sf_const_m0 (void)
+{
+ return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */
+}
+
+vector float
+v4sf_splats_1 (void)
+{
+ return vec_splats (1.0f); /* XXSPLTIW. */
+}
+
+vector float
+v4sf_splats_nan (void)
+{
+ return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */
+}
+
+vector float
+v4sf_splats_inf (void)
+{
+ return vec_splats (__builtin_inff ()); /* XXSPLTIW. */
+}
+
+vector float
+v8hi_splats_m0 (void)
+{
+ return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */
+/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */
+/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
+/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
new file mode 100644
index 00000000000..da909e948b2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c
@@ -0,0 +1,51 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
+
+#include <altivec.h>
+
+/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure
+ the power9 support (XXSPLTIB/VEXTSB2W) is not done. */
+
+vector int
+v4si_const_1 (void)
+{
+ return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */
+}
+
+vector int
+v4si_const_126 (void)
+{
+ return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */
+}
+
+vector int
+v4si_const_1023 (void)
+{
+ return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
+}
+
+vector int
+v4si_splats_1 (void)
+{
+ return vec_splats (1); /* VSLTPISW. */
+}
+
+vector int
+v4si_splats_126 (void)
+{
+ return vec_splats (126); /* XXSPLTIW. */
+}
+
+vector int
+v8hi_splats_1023 (void)
+{
+ return vec_splats (1023); /* XXSPLTIW. */
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */
+/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
+/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
+/* { dg-final { scan-assembler-not {\mplxv\M} } } */
diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
new file mode 100644
index 00000000000..290e05d4a64
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c
@@ -0,0 +1,62 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target power10_ok } */
+/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */
+
+#include <altivec.h>
+
+/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure
+ the power9 support (XXSPLTIB/VUPKLSB) is not done. */
+
+vector short
+v8hi_const_1 (void)
+{
+ return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */
+}
+
+vector short
+v8hi_const_126 (void)
+{
+ return (vector short) { 126, 126, 126, 126,
+ 126, 126, 126, 126 }; /* XXSPLTIW. */
+}
+
+vector short
+v8hi_const_1023 (void)
+{
+ return (vector short) { 1023, 1023, 1023, 1023,
+ 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */
+}
+
+vector short
+v8hi_splats_1 (void)
+{
+ return vec_splats ((short)1); /* VSLTPISH. */
+}
+
+vector short
+v8hi_splats_126 (void)
+{
+ return vec_splats ((short)126); /* XXSPLTIW. */
+}
+
+vector short
+v8hi_splats_1023 (void)
+{
+ return vec_splats ((short)1023); /* XXSPLTIW. */
+}
+
+/* Test that we can optimiza V8HI where all of the even elements are the same
+ and all of the odd elements are the same. */
+vector short
+v8hi_const_1023_1000 (void)
+{
+ return (vector short) { 1023, 1000, 1023, 1000,
+ 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */
+}
+
+/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */
+/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */
+/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */
+/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */
+/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */
+/* { dg-final { scan-assembler-not {\mplxv\M} } } */
next reply other threads:[~2021-10-14 18:15 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-10-14 18:15 Michael Meissner [this message]
-- strict thread matches above, loose matches on Subject: below --
2021-10-21 2:53 Michael Meissner
2021-10-21 2:38 Michael Meissner
2021-10-21 0:40 Michael Meissner
2021-10-20 22:58 Michael Meissner
2021-10-20 22:24 Michael Meissner
2021-10-18 18:51 Michael Meissner
2021-10-18 18:47 Michael Meissner
2021-10-16 1:36 Michael Meissner
2021-10-15 15:15 Michael Meissner
2021-10-15 5:29 Michael Meissner
2021-10-15 4:16 Michael Meissner
2021-10-14 13:39 Michael Meissner
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20211014181503.F0C353858412@sourceware.org \
--to=meissner@gcc.gnu.org \
--cc=gcc-cvs@gcc.gnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).