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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work071)] Revert patches. Date: Mon, 18 Oct 2021 18:49:50 +0000 (GMT) [thread overview] Message-ID: <20211018184950.4E8BF3858C60@sourceware.org> (raw) https://gcc.gnu.org/g:d8efdc5887a864b8842e7d4053d9cff4e5324a64 commit d8efdc5887a864b8842e7d4053d9cff4e5324a64 Author: Michael Meissner <meissner@linux.ibm.com> Date: Mon Oct 18 14:49:07 2021 -0400 Revert patches. 2021-10-18 Michael Meissner <meissner@linux.ibm.com> gcc/ Revert patches. * config/rs6000/predicates.md (easy_fp_constant): Add support for XXSPLTIW. (vsx_prefixed_constant): Likewise. (easy_vector_constant): Likewise. * config/rs6000/rs6000-protos.h (vec_const_use_xxspltiw): New declaration. * config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate XXSPLTIW, don't do XXSPLTIB and sign extend. (output_vec_const_move): Add support for XXSPLTIW. (prefixed_xxsplti_p): Recognize XXSPLTIW instructions as prefixed. (vec_const_use_xxspltiw): New function. * config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec. (xxspltiw_<mode>_internal): New insns. (VSX prefixed constant splitter): Add XXSPLTIW support. * config/rs6000/rs6000.opt (-mxxspltiw): New debug switch. * config/rs6000/vsx.md (vsx_mov<mode>_64bit): Update comment. (vsx_mov<mode>_32bit): Likewise. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-v16qi.c: New test. * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. * gcc.target/powerpc/vec-splati-runnable.c: Update insn count. Diff: --- gcc/config/rs6000/predicates.md | 14 ----- gcc/config/rs6000/rs6000-protos.h | 1 - gcc/config/rs6000/rs6000.c | 43 -------------- gcc/config/rs6000/rs6000.md | 17 ------ gcc/config/rs6000/rs6000.opt | 4 -- .../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 --------- .../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 ---------------------- .../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 ---------------- .../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 -------------------- .../gcc.target/powerpc/vec-splati-runnable.c | 2 +- 10 files changed, 1 insertion(+), 287 deletions(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 40c4cba68ff..4b2bbdf40e8 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -608,9 +608,6 @@ { if (vec_const_use_xxspltidp (&vec_const)) return true; - - if (vec_const_use_xxspltiw (&vec_const)) - return true; } /* Otherwise consider floating point constants hard, so that the @@ -647,14 +644,6 @@ if (!vec_const_to_bytes (op, mode, &vec_const)) return false; - /* If we can generate the constant with 1-2 Altivec instructions, don't - generate a prefixed instruction. */ - if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode)) - return false; - - if (vec_const_use_xxspltiw (&vec_const)) - return true; - if (vec_const_use_xxspltidp (&vec_const)) return true; @@ -717,9 +706,6 @@ { if (vec_const_use_xxspltidp (&vec_const)) return true; - - if (vec_const_use_xxspltiw (&vec_const)) - return true; } return easy_altivec_constant (op, mode); diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index b12f6b10c13..8eef955237a 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -249,7 +249,6 @@ typedef struct { extern bool vec_const_to_bytes (rtx, machine_mode, rs6000_vec_const *); extern bool vec_const_use_xxspltidp (rs6000_vec_const *); -extern bool vec_const_use_xxspltiw (rs6000_vec_const *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 20226169ba2..353ec2b572d 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op, else if (IN_RANGE (value, -1, 0)) *num_insns_ptr = 1; - /* If we can generate XXSPLTIW, don't generate XXSPLTIB and a sign extend - operation. */ - else if (vsx_prefixed_constant (op, mode)) - return false; - else *num_insns_ptr = 2; @@ -7003,12 +6998,6 @@ output_vec_const_move (rtx *operands) operands[2] = GEN_INT (vec_const.xxspltidp_immediate); return "xxspltidp %x0,%2"; } - - if (vec_const_use_xxspltiw (&vec_const)) - { - operands[2] = GEN_INT (vec_const.words[0]); - return "xxspltiw %x0,%2"; - } } if (TARGET_P9_VECTOR @@ -28795,38 +28784,6 @@ vec_const_use_xxspltidp (rs6000_vec_const *vec_const) return true; } -/* Determine if a vector constant can be loaded with XXSPLTIW. */ - -bool -vec_const_use_xxspltiw (rs6000_vec_const *vec_const) -{ - if (!TARGET_XXSPLTIW || !TARGET_PREFIXED || !TARGET_VSX) - return false; - - if (!vec_const->all_words_same) - return false; - - /* If we can use XXSPLTIB, don't generate XXSPLTIW. */ - if (vec_const->all_bytes_same) - return false; - - /* See if we can use VSPLTISH or VSPLTISW. */ - if (vec_const->all_half_words_same) - { - unsigned short h_word = vec_const->half_words[0]; - short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000; - if (EASY_VECTOR_15 (sign_h_word)) - return false; - } - - unsigned int word = vec_const->words[0]; - int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000; - if (EASY_VECTOR_15 (sign_word)) - return false; - - return true; -} - /* Convert a vector constant to an internal structure, breaking it out to bytes, half words, words, and double words. Return true if we have successfully broken it out. */ diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 1963eb01ed7..5d830e0db15 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -157,7 +157,6 @@ UNSPEC_HASHST UNSPEC_HASHCHK UNSPEC_XXSPLTIDP_CONST - UNSPEC_XXSPLTIW_CONST ]) ;; @@ -8233,15 +8232,6 @@ [(set_attr "type" "vecperm") (set_attr "prefixed" "yes")]) -(define_insn "xxspltiw_<mode>_internal" - [(set (match_operand:SFDF 0 "register_operand" "=wa") - (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] - UNSPEC_XXSPLTIW_CONST))] - "TARGET_POWER10" - "xxspltidp %x0,%1" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - (define_split [(set (match_operand:SFDF 0 "vsx_register_operand") (match_operand:SFDF 1 "vsx_prefixed_constant"))] @@ -8262,13 +8252,6 @@ DONE; } - if (vec_const_use_xxspltiw (&vec_const)) - { - rtx imm = GEN_INT (vec_const.words[0]); - emit_insn (gen_xxspltiw_<mode>_internal (dest, imm)); - DONE; - } - else gcc_unreachable (); }) diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 332f61be0ba..1d7ce4cc94a 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -644,10 +644,6 @@ mxxspltidp Target Undocumented Var(TARGET_XXSPLTIDP) Init(1) Save Generate (do not generate) XXSPLTIDP instructions. -mxxspltiw -Target Undocumented Var(TARGET_XXSPLTIW) Init(1) Save -Generate (do not generate) XXSPLTIW instructions. - -param=rs6000-density-pct-threshold= Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param When costing for loop vectorization, we probably need to penalize the loop body diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c deleted file mode 100644 index 2707d86e6fd..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include <altivec.h> - -/* Test whether XXSPLTIW is generated for V16HI vector constants where the - first 4 elements are the same as the next 4 elements, etc. */ - -vector unsigned char -v16qi_const_1 (void) -{ - return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */ -} - -vector unsigned char -v16qi_const_2 (void) -{ - return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4, - 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c deleted file mode 100644 index 05d4ee3f5cb..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c +++ /dev/null @@ -1,67 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include <altivec.h> - -/* Test whether XXSPLTIW is generated for V4SF vector constants. */ - -vector float -v4sf_const_1 (void) -{ - return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_nan (void) -{ - return (vector float) { __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf ("") }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_inf (void) -{ - return (vector float) { __builtin_inff (), - __builtin_inff (), - __builtin_inff (), - __builtin_inff () }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_m0 (void) -{ - return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */ -} - -vector float -v4sf_splats_1 (void) -{ - return vec_splats (1.0f); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_nan (void) -{ - return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_inf (void) -{ - return vec_splats (__builtin_inff ()); /* XXSPLTIW. */ -} - -vector float -v8hi_splats_m0 (void) -{ - return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */ -/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c deleted file mode 100644 index da909e948b2..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include <altivec.h> - -/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure - the power9 support (XXSPLTIB/VEXTSB2W) is not done. */ - -vector int -v4si_const_1 (void) -{ - return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */ -} - -vector int -v4si_const_126 (void) -{ - return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector int -v4si_const_1023 (void) -{ - return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector int -v4si_splats_1 (void) -{ - return vec_splats (1); /* VSLTPISW. */ -} - -vector int -v4si_splats_126 (void) -{ - return vec_splats (126); /* XXSPLTIW. */ -} - -vector int -v8hi_splats_1023 (void) -{ - return vec_splats (1023); /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c deleted file mode 100644 index 290e05d4a64..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c +++ /dev/null @@ -1,62 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2 -mxxspltiw" } */ - -#include <altivec.h> - -/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure - the power9 support (XXSPLTIB/VUPKLSB) is not done. */ - -vector short -v8hi_const_1 (void) -{ - return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */ -} - -vector short -v8hi_const_126 (void) -{ - return (vector short) { 126, 126, 126, 126, - 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector short -v8hi_const_1023 (void) -{ - return (vector short) { 1023, 1023, 1023, 1023, - 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1 (void) -{ - return vec_splats ((short)1); /* VSLTPISH. */ -} - -vector short -v8hi_splats_126 (void) -{ - return vec_splats ((short)126); /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1023 (void) -{ - return vec_splats ((short)1023); /* XXSPLTIW. */ -} - -/* Test that we can optimiza V8HI where all of the even elements are the same - and all of the odd elements are the same. */ -vector short -v8hi_const_1023_1000 (void) -{ - return (vector short) { 1023, 1000, 1023, 1000, - 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */ -/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c index 6c01666b625..5f84930e1a7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c @@ -149,7 +149,7 @@ main (int argc, char *argv []) return 0; } -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */ /* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */
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