From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id C770D3858D39; Thu, 21 Oct 2021 02:20:30 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org C770D3858D39 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work071)] Add LXVKQ support. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work071 X-Git-Oldrev: c876b8955367d58a5631b9e71e1888d5854fcae8 X-Git-Newrev: 57878eabefae88ecb4b6a65a7cee57e00146b261 Message-Id: <20211021022030.C770D3858D39@sourceware.org> Date: Thu, 21 Oct 2021 02:20:30 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 02:20:30 -0000 https://gcc.gnu.org/g:57878eabefae88ecb4b6a65a7cee57e00146b261 commit 57878eabefae88ecb4b6a65a7cee57e00146b261 Author: Michael Meissner Date: Wed Oct 20 22:20:10 2021 -0400 Add LXVKQ support. This patch adds support to generate the LXVKQ instruction to load specific IEEE-128 floating point constants. Compared to the last time I submitted this patch, I modified it so that it uses the bit pattern of the vector to see if it can generate the LXVKQ instruction. This means on a little endian Power system, the following code will generate a LXVKQ 34,16 instruction: vector long long foo (void) { return (vector long long) { 0x0000000000000000, 0x8000000000000000 }; } because that vector pattern is the same bit pattern as -0.0F128. 2021-10-20 Michael Meissner gcc/ * config/rs6000/constraints.md (eQ): New constraint. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating the LXVKQ instruction. (easy_vector_constant_ieee128): New predicate. (easy_vector_constant): Add support for generating the LXVKQ instruction. * config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New declaration. * config/rs6000/rs6000.c (output_vec_const_move): Add support for generating LXVKQ. (constant_generates_lxvkq): New function. * config/rs6000/rs6000.opt (-mieee128-constant): New debug option. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for generating LXVKQ. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eQ constraint. gcc/testsuite/ * gcc.target/powerpc/float128-constant.c: New test. Diff: --- gcc/config/rs6000/constraints.md | 6 + gcc/config/rs6000/predicates.md | 23 +++ gcc/config/rs6000/rs6000-protos.h | 1 + gcc/config/rs6000/rs6000.c | 64 ++++++++- gcc/config/rs6000/rs6000.opt | 4 + gcc/config/rs6000/vsx.md | 28 ++-- gcc/doc/md.texi | 4 + .../gcc.target/powerpc/float128-constant.c | 160 +++++++++++++++++++++ 8 files changed, 275 insertions(+), 15 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 7d594872a78..906fa44bec3 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -219,6 +219,12 @@ "A constant that can be loaded into a VSX register with one prefixed insn." (match_operand 0 "vsx_prefixed_constant")) +;; A TF/KF scalar constant or a vector constant that can load certain IEEE +;; 128-bit constants into vector registers using LXVKQ. +(define_constraint "eQ" + "An IEEE 128-bit constant that can be loaded into VSX registers." + (match_operand 0 "easy_vector_constant_ieee128")) + ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 4b07850eb64..46ea61d64ac 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -606,6 +606,9 @@ if (TARGET_POWER10 && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES)) { + if (constant_generates_lxvkq (&vsx_const)) + return true; + if (constant_generates_xxspltidp (&vsx_const)) return true; @@ -660,6 +663,23 @@ return false; }) +;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded +;; via the LXVKQ instruction. + +(define_predicate "easy_vector_constant_ieee128" + (match_code "const_vector,const_double") +{ + rs6000_const vsx_const; + + /* Can we generate the LXVKQ instruction? */ + if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 + || !TARGET_VSX) + return false; + + return (constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT) + && constant_generates_lxvkq (&vsx_const)); +}) + ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. @@ -710,6 +730,9 @@ if (TARGET_POWER10 && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT)) { + if (constant_generates_lxvkq (&vsx_const)) + return true; + if (constant_generates_xxspltidp (&vsx_const)) return true; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 0b93bc3cc0e..20cb092e159 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -260,6 +260,7 @@ extern bool constant_to_bytes (rtx, machine_mode, rs6000_const *, rs6000_const_splat); extern unsigned constant_generates_xxspltidp (rs6000_const *); extern unsigned constant_generates_xxspltiw (rs6000_const *); +extern unsigned constant_generates_lxvkq (rs6000_const *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4f24d9491da..282505471ff 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7001,7 +7001,14 @@ output_vec_const_move (rtx *operands) if (constant_to_bytes (vec, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES)) { - unsigned imm = constant_generates_xxspltidp (&vsx_const); + unsigned imm = constant_generates_lxvkq (&vsx_const); + if (imm) + { + operands[2] = GEN_INT (imm); + return "lxvkq %x0,%2"; + } + + imm = constant_generates_xxspltidp (&vsx_const); if (imm) { operands[2] = GEN_INT (imm); @@ -29054,6 +29061,61 @@ constant_generates_xxspltiw (rs6000_const *vsx_const) return vsx_const->words[0]; } +/* Determine if an IEEE 128-bit constant can be loaded with LXVKQ. Return zero + if the LXVKQ instruction cannot be used. Otherwise return the immediate + value to be used with the LXVKQ instruction. */ + +unsigned +constant_generates_lxvkq (rs6000_const *vsx_const) +{ + /* Is the instruction supported with power10 code generation, IEEE 128-bit + floating point hardware and VSX registers are available. */ + if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 + || !TARGET_VSX) + return 0; + + /* Only recognize LXVKQ for 16-byte (4 word) vector constants. */ + unsigned total_size = vsx_const->total_size; + if (total_size != 16) + return 0; + + /* Verify that all of the bottom 3 words in the constants loaded by the + LXVKQ instruction are zero. */ + if (vsx_const->words[1] != 0 + || vsx_const->words[2] != 0 + || vsx_const->words[3] != 0) + return 0; + + /* See if we have a match. */ + switch (vsx_const->words[0]) + { + case 0x3FFF0000U: return 1; /* IEEE 128-bit +1.0. */ + case 0x40000000U: return 2; /* IEEE 128-bit +2.0. */ + case 0x40008000U: return 3; /* IEEE 128-bit +3.0. */ + case 0x40010000U: return 4; /* IEEE 128-bit +4.0. */ + case 0x40014000U: return 5; /* IEEE 128-bit +5.0. */ + case 0x40018000U: return 6; /* IEEE 128-bit +6.0. */ + case 0x4001C000U: return 7; /* IEEE 128-bit +7.0. */ + case 0x7FFF0000U: return 8; /* IEEE 128-bit +Infinity. */ + case 0x7FFF8000U: return 9; /* IEEE 128-bit quiet NaN. */ + case 0x80000000U: return 16; /* IEEE 128-bit -0.0. */ + case 0xBFFF0000U: return 17; /* IEEE 128-bit -1.0. */ + case 0xC0000000U: return 18; /* IEEE 128-bit -2.0. */ + case 0xC0008000U: return 19; /* IEEE 128-bit -3.0. */ + case 0xC0010000U: return 20; /* IEEE 128-bit -4.0. */ + case 0xC0014000U: return 21; /* IEEE 128-bit -5.0. */ + case 0xC0018000U: return 22; /* IEEE 128-bit -6.0. */ + case 0xC001C000U: return 23; /* IEEE 128-bit -7.0. */ + case 0xFFFF0000U: return 24; /* IEEE 128-bit -Infinity. */ + + /* anything else cannot be loaded. */ + default: + break; + } + + return 0; +} + struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index ec607a7aee7..3ddac80289c 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -648,6 +648,10 @@ msplat-word-constant Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save Generate (do not generate) code that uses the XXSPLTIW instruction. +mieee128-constant +Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save +Generate (do not generate) code that uses the LXVKQ instruction. + -param=rs6000-density-pct-threshold= Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param When costing for loop vectorization, we probably need to penalize the loop body diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index 0ceecc1975c..ce8402101ef 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1192,19 +1192,19 @@ ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW -;; XXLSPLTI* +;; XXLSPLTI* LXVKQ ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, - wa, + wa, wa, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, - eP, + eP, eQ, ?jwM, W, , v, wZ"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) @@ -1216,46 +1216,46 @@ [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, store, load, store, *, vecsimple, vecsimple, - vecperm, + vecperm, vecperm, vecsimple, *, *, vecstore, vecload") (set_attr "num_insns" "*, *, *, 2, *, 2, 2, 2, 2, 2, *, *, - *, + *, *, *, 5, 2, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, 2, 2, 2, 2, *, *, - *, + *, *, *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, - *, + *, *, *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, - p10, + p10, p10, , *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move ;; XXSPLTIB VSPLTISW VSX 0/-1 -;; XXSPLTI* +;; XXSPLTI* LXVKQ ;; VMX const GPR const ;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , wa, v, ?wa, - wa, + wa, wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, wE, jwM, ?jwM, - eP, + eP, eQ, W, , v, wZ"))] @@ -1268,19 +1268,19 @@ [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, vecsimple, vecsimple, vecsimple, - vecperm, + vecperm, vecperm, *, *, vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, *, *, *, - *, + *, *, 20, 16, *, *") (set_attr "isa" ", , , *, *, *, p9v, *, , - p10, + p10, p10, *, *, *, *")]) diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 13b56279565..41a568b7d4e 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3340,6 +3340,10 @@ A signed 34-bit integer constant if prefixed instructions are supported. A scalar floating point constant or a vector constant that can be loaded with one prefixed instruction to a VSX register. +@item eQ +An IEEE 128-bit constant that can be loaded into a VSX register with a +single instruction. + @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c new file mode 100644 index 00000000000..e3286a786a5 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/float128-constant.c @@ -0,0 +1,160 @@ +/* { dg-require-effective-target ppc_float128_hw } */ +/* { dg-require-effective-target power10_ok } */ +/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ + +/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit + constants. */ + +_Float128 +return_0 (void) +{ + return 0.0f128; /* XXSPLTIB 34,0. */ +} + +_Float128 +return_1 (void) +{ + return 1.0f128; /* LXVKQ 34,1. */ +} + +_Float128 +return_2 (void) +{ + return 2.0f128; /* LXVKQ 34,2. */ +} + +_Float128 +return_3 (void) +{ + return 3.0f128; /* LXVKQ 34,3. */ +} + +_Float128 +return_4 (void) +{ + return 4.0f128; /* LXVKQ 34,4. */ +} + +_Float128 +return_5 (void) +{ + return 5.0f128; /* LXVKQ 34,5. */ +} + +_Float128 +return_6 (void) +{ + return 6.0f128; /* LXVKQ 34,6. */ +} + +_Float128 +return_7 (void) +{ + return 7.0f128; /* LXVKQ 34,7. */ +} + +_Float128 +return_m0 (void) +{ + return -0.0f128; /* LXVKQ 34,16. */ +} + +_Float128 +return_m1 (void) +{ + return -1.0f128; /* LXVKQ 34,17. */ +} + +_Float128 +return_m2 (void) +{ + return -2.0f128; /* LXVKQ 34,18. */ +} + +_Float128 +return_m3 (void) +{ + return -3.0f128; /* LXVKQ 34,19. */ +} + +_Float128 +return_m4 (void) +{ + return -4.0f128; /* LXVKQ 34,20. */ +} + +_Float128 +return_m5 (void) +{ + return -5.0f128; /* LXVKQ 34,21. */ +} + +_Float128 +return_m6 (void) +{ + return -6.0f128; /* LXVKQ 34,22. */ +} + +_Float128 +return_m7 (void) +{ + return -7.0f128; /* LXVKQ 34,23. */ +} + +_Float128 +return_inf (void) +{ + return __builtin_inff128 (); /* LXVKQ 34,8. */ +} + +_Float128 +return_minf (void) +{ + return - __builtin_inff128 (); /* LXVKQ 34,24. */ +} + +_Float128 +return_nan (void) +{ + return __builtin_nanf128 (""); /* LXVKQ 34,9. */ +} + +/* Note, the following NaNs should not generate a LXVKQ instruction. */ +_Float128 +return_mnan (void) +{ + return - __builtin_nanf128 (""); /* PLXV 34,... */ +} + +_Float128 +return_nan2 (void) +{ + return __builtin_nanf128 ("1"); /* PLXV 34,... */ +} + +_Float128 +return_nans (void) +{ + return __builtin_nansf128 (""); /* PLXV 34,... */ +} + +vector long long +return_longlong_neg_0 (void) +{ + /* This vector is the same pattern as -0.0F128. */ +#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#define FIRST 0x8000000000000000 +#define SECOND 0x0000000000000000 + +#else +#define FIRST 0x0000000000000000 +#define SECOND 0x8000000000000000 +#endif + + return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */ +} + +/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */ +/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ +