From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1005) id 703EC3858D39; Thu, 21 Oct 2021 02:27:05 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 703EC3858D39 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Michael Meissner To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work071)] Revert patches. X-Act-Checkin: gcc X-Git-Author: Michael Meissner X-Git-Refname: refs/users/meissner/heads/work071 X-Git-Oldrev: 57878eabefae88ecb4b6a65a7cee57e00146b261 X-Git-Newrev: c0e1470ccd169cdc4781f46f621a7c8535f4fbb2 Message-Id: <20211021022705.703EC3858D39@sourceware.org> Date: Thu, 21 Oct 2021 02:27:05 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 21 Oct 2021 02:27:05 -0000 https://gcc.gnu.org/g:c0e1470ccd169cdc4781f46f621a7c8535f4fbb2 commit c0e1470ccd169cdc4781f46f621a7c8535f4fbb2 Author: Michael Meissner Date: Wed Oct 20 22:25:12 2021 -0400 Revert patches. 2021-10-20 Michael Meissner gcc/ Revert patches. * config/rs6000/constraints.md (eQ): New constraint. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating the LXVKQ instruction. (easy_vector_constant_ieee128): New predicate. (easy_vector_constant): Add support for generating the LXVKQ instruction. * config/rs6000/rs6000-protos.h (constant_generates_lxvkq): New declaration. * config/rs6000/rs6000.c (output_vec_const_move): Add support for generating LXVKQ. (constant_generates_lxvkq): New function. * config/rs6000/rs6000.opt (-mieee128-constant): New debug option. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for generating LXVKQ. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eQ constraint. gcc/testsuite/ Revert patches. * gcc.target/powerpc/float128-constant.c: New test. 2021-10-20 Michael Meissner gcc/ Revert patches. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating XXSPLTIW. (vsx_prefixed_constant): Likewise. (easy_vector_constant): Likewise. * config/rs6000/rs6000-protos.h (constant_generates_xxspltiw): New declaration. * config/rs6000/rs6000.c (xxspltib_constant_p): If we can generate XXSPLTIW, don't do XXSPLTIB and sign extend. (output_vec_const_move): Add support for XXSPLTIW. (prefixed_xxsplti_p): Recognize XXSPLTIW instructions as prefixed. (constant_generates_xxspltiw): New function. * config/rs6000/rs6000.md (UNSPEC_XXSPLTIW_CONST): New unspec. (xxspltiw__internal): New insns. (VSX prefixed constant splitter): Add XXSPLTIW support. * config/rs6000/rs6000.opt (-msplat-word-constant): New debug switch. * config/rs6000/vsx.md (vsx_mov_64bit): Update comment. (vsx_mov_32bit): Likewise. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-v16qi.c: New test. * gcc.target/powerpc/vec-splat-constant-v4sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v4si.c: New test. * gcc.target/powerpc/vec-splat-constant-v8hi.c: New test. * gcc.target/powerpc/vec-splati-runnable.c: Update insn count. 2021-10-20 Michael Meissner gcc/ Revert patches. * config/rs6000/constraints.md (eP): New constraint. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating XXSPLTIDP. (vsx_prefixed_constant): New predicate. (easy_vector_constant): Add support for generating XXSPLTIDP. * config/rs6000/rs6000-protos.h (prefixed_xxsplti_p): New declaration. (constant_generates_xxspltidp): New declaration. * config/rs6000/rs6000.c (prefixed_xxsplti_p): New function. (constant_generates_xxspltidp): New function. * config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec. (prefixed attribute): Add support for prefixed instructions to load constants into VSX registers. (movsf_hardfloat): Add support for XXSPLTIDP. (mov_hardfloat32, FMOVE64 iterator): Likewise. (mov_hardfloat64, FMOVE64 iterator): Likewise. (xxspltidp__internal): New insns. (splitter for VSX prefix constants): New splitters. * config/rs6000/rs6000.opt (-msplat-float-constant): New debug option. * config/rs6000/vsx.md (vsx_mov_64bit): Add support for XXSPLTIDP. (vsx_mov_32bit): Likewise. * doc/md.texi (PowerPC and IBM RS6000 constraints): Document the eP constraint. gcc/testsuite/ Revert patches. * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn regex for power10. * gcc.target/powerpc/vec-splat-constant-df.c: New test. * gcc.target/powerpc/vec-splat-constant-sf.c: New test. * gcc.target/powerpc/vec-splat-constant-v2df.c: New test. * gcc.target/powerpc/vec-splat-constant-v2di.c: New test. * gcc.target/powerpc/vec-splati-runnable.c: Update insn counts. 2021-10-20 Michael Meissner gcc/ Revert patches. * config/rs6000/rs6000-protos.h (RS6000_CONST_*): New macros. (rs6000_const_splat): New enum type. (rs6000_const): New structure type. (constant_to_bytes): New declaration. * config/rs6000/rs6000.c (constant_integer_to_bytes): New helper function. (constant_floating_point_to_bytes): New helper function. (constant_to_bytes): New function. Diff: --- gcc/config/rs6000/constraints.md | 12 - gcc/config/rs6000/predicates.md | 87 ---- gcc/config/rs6000/rs6000-protos.h | 39 -- gcc/config/rs6000/rs6000.c | 530 --------------------- gcc/config/rs6000/rs6000.md | 102 +--- gcc/config/rs6000/rs6000.opt | 12 - gcc/config/rs6000/vsx.md | 32 +- gcc/doc/md.texi | 8 - .../gcc.target/powerpc/float128-constant.c | 160 ------- .../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +- .../gcc.target/powerpc/vec-splat-constant-df.c | 60 --- .../gcc.target/powerpc/vec-splat-constant-sf.c | 60 --- .../gcc.target/powerpc/vec-splat-constant-v16qi.c | 27 -- .../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 --- .../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 -- .../gcc.target/powerpc/vec-splat-constant-v4sf.c | 67 --- .../gcc.target/powerpc/vec-splat-constant-v4si.c | 51 -- .../gcc.target/powerpc/vec-splat-constant-v8hi.c | 62 --- .../gcc.target/powerpc/vec-splati-runnable.c | 4 +- 19 files changed, 30 insertions(+), 1406 deletions(-) diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md index 906fa44bec3..c8cff1a3038 100644 --- a/gcc/config/rs6000/constraints.md +++ b/gcc/config/rs6000/constraints.md @@ -213,18 +213,6 @@ "A signed 34-bit integer constant if prefixed instructions are supported." (match_operand 0 "cint34_operand")) -;; A SF/DF scalar constant or a vector constant that can be loaded into vector -;; registers with one prefixed instruction such as XXSPLTIDP. -(define_constraint "eP" - "A constant that can be loaded into a VSX register with one prefixed insn." - (match_operand 0 "vsx_prefixed_constant")) - -;; A TF/KF scalar constant or a vector constant that can load certain IEEE -;; 128-bit constants into vector registers using LXVKQ. -(define_constraint "eQ" - "An IEEE 128-bit constant that can be loaded into VSX registers." - (match_operand 0 "easy_vector_constant_ieee128")) - ;; Floating-point constraints. These two are defined so that insn ;; length attributes can be calculated exactly. diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index 46ea61d64ac..956e42bc514 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -601,21 +601,6 @@ if (TARGET_VSX && op == CONST0_RTX (mode)) return 1; - /* Constants that can be generated with ISA 3.1 instructions are easy. */ - rs6000_const vsx_const; - if (TARGET_POWER10 - && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES)) - { - if (constant_generates_lxvkq (&vsx_const)) - return true; - - if (constant_generates_xxspltidp (&vsx_const)) - return true; - - if (constant_generates_xxspltiw (&vsx_const)) - return true; - } - /* Otherwise consider floating point constants hard, so that the constant gets pushed to memory during the early RTL phases. This has the advantage that double precision constants that can be @@ -624,62 +609,6 @@ return 0; }) -;; Return 1 if the operand is a 64-bit floating point scalar constant or a -;; vector constant that can be loaded to a VSX register with one prefixed -;; instruction, such as XXSPLTIDP or XXSPLTIW. -;; -;; In addition regular constants, we also recognize constants formed with the -;; VEC_DUPLICATE insn from scalar constants. -;; -;; We don't handle scalar integer constants here because the assumption is the -;; normal integer constants will be loaded into GPR registers. For the -;; constants that need to be loaded into vector registers, the instructions -;; don't work well with TImode variables assigned a constant. This is because -;; the 64-bit scalar constants are splatted into both halves of the register. - -(define_predicate "vsx_prefixed_constant" - (match_code "const_double,const_vector,vec_duplicate") -{ - /* If we can generate the constant with 1-2 Altivec instructions, don't - generate a prefixed instruction. */ - if (CONST_VECTOR_P (op) && easy_altivec_constant (op, mode)) - return false; - - /* Do we have prefixed instructions and are VSX registers available? Is the - constant recognized? */ - if (!TARGET_PREFIXED || !TARGET_VSX) - return false; - - rs6000_const vsx_const; - if (!constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES)) - return false; - - if (constant_generates_xxspltidp (&vsx_const)) - return true; - - if (constant_generates_xxspltiw (&vsx_const)) - return true; - - return false; -}) - -;; Return 1 if the operand is a special IEEE 128-bit value that can be loaded -;; via the LXVKQ instruction. - -(define_predicate "easy_vector_constant_ieee128" - (match_code "const_vector,const_double") -{ - rs6000_const vsx_const; - - /* Can we generate the LXVKQ instruction? */ - if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 - || !TARGET_VSX) - return false; - - return (constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT) - && constant_generates_lxvkq (&vsx_const)); -}) - ;; Return 1 if the operand is a constant that can loaded with a XXSPLTIB ;; instruction and then a VUPKHSB, VECSB2W or VECSB2D instruction. @@ -724,22 +653,6 @@ if (zero_constant (op, mode) || all_ones_constant (op, mode)) return true; - /* Constants that can be generated with ISA 3.1 instructions are - easy. */ - rs6000_const vsx_const; - if (TARGET_POWER10 - && constant_to_bytes (op, mode, &vsx_const, RS6000_CONST_NO_SPLAT)) - { - if (constant_generates_lxvkq (&vsx_const)) - return true; - - if (constant_generates_xxspltidp (&vsx_const)) - return true; - - if (constant_generates_xxspltiw (&vsx_const)) - return true; - } - if (TARGET_P9_VECTOR && xxspltib_constant_p (op, mode, &num_insns, &value)) return true; diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 20cb092e159..14f6b313105 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -198,7 +198,6 @@ enum non_prefixed_form reg_to_non_prefixed (rtx reg, machine_mode mode); extern bool prefixed_load_p (rtx_insn *); extern bool prefixed_store_p (rtx_insn *); extern bool prefixed_paddi_p (rtx_insn *); -extern bool prefixed_xxsplti_p (rtx_insn *); extern void rs6000_asm_output_opcode (FILE *); extern void output_pcrel_opt_reloc (rtx); extern void rs6000_final_prescan_insn (rtx_insn *, rtx [], int); @@ -223,44 +222,6 @@ address_is_prefixed (rtx addr, return (iform == INSN_FORM_PREFIXED_NUMERIC || iform == INSN_FORM_PCREL_LOCAL); } - -/* Functions and data structures relating to constants that are converted to - byte, half-word, word, and double-word values. All fields are kept in big - endian order. */ -#define RS6000_CONST_MAX_BITS 128 /* Largest constant size. */ -#define RS6000_CONST_MAX_BYTES (RS6000_CONST_MAX_BITS / 8) -#define RS6000_CONST_MAX_HALF_WORDS (RS6000_CONST_MAX_BITS / 16) -#define RS6000_CONST_MAX_WORDS (RS6000_CONST_MAX_BITS / 32) -#define RS6000_CONST_MAX_DOUBLE_WORDS (RS6000_CONST_MAX_BITS / 64) - -/* If the constant is small, whether we will splat the constant to fill a - vector. */ -typedef enum { - RS6000_CONST_NO_SPLAT, /* Do not splat the constant. */ - RS6000_CONST_SPLAT_16_BYTES /* Splat to fill 16-bytes. */ -} rs6000_const_splat; - -typedef struct { - /* Constant as various sized items. */ - unsigned HOST_WIDE_INT double_words[RS6000_CONST_MAX_DOUBLE_WORDS]; - unsigned int words[RS6000_CONST_MAX_WORDS]; - unsigned short half_words[RS6000_CONST_MAX_HALF_WORDS]; - unsigned char bytes[RS6000_CONST_MAX_BYTES]; - - unsigned total_size; /* Size in bytes of the constant. */ - unsigned original_size; /* Size before a possible splat. */ - bool fp_constant_p; /* Is the constant floating point? */ - bool all_double_words_same; /* Are the double words all equal? */ - bool all_words_same; /* Are the words all equal? */ - bool all_half_words_same; /* Are the halft words all equal? */ - bool all_bytes_same; /* Are the bytes all equal? */ -} rs6000_const; - -extern bool constant_to_bytes (rtx, machine_mode, rs6000_const *, - rs6000_const_splat); -extern unsigned constant_generates_xxspltidp (rs6000_const *); -extern unsigned constant_generates_xxspltiw (rs6000_const *); -extern unsigned constant_generates_lxvkq (rs6000_const *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 282505471ff..acba4d9f26c 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -6939,11 +6939,6 @@ xxspltib_constant_p (rtx op, else if (IN_RANGE (value, -1, 0)) *num_insns_ptr = 1; - /* If we can generate XXSPLTIW or XXSPLTIDP, don't generate XXSPLTIB and a - sign extend operation. */ - else if (vsx_prefixed_constant (op, mode)) - return false; - else *num_insns_ptr = 2; @@ -6995,35 +6990,6 @@ output_vec_const_move (rtx *operands) gcc_unreachable (); } - if (TARGET_PREFIXED) - { - rs6000_const vsx_const; - if (constant_to_bytes (vec, mode, &vsx_const, - RS6000_CONST_SPLAT_16_BYTES)) - { - unsigned imm = constant_generates_lxvkq (&vsx_const); - if (imm) - { - operands[2] = GEN_INT (imm); - return "lxvkq %x0,%2"; - } - - imm = constant_generates_xxspltidp (&vsx_const); - if (imm) - { - operands[2] = GEN_INT (imm); - return "xxspltidp %x0,%2"; - } - - imm = constant_generates_xxspltiw (&vsx_const); - if (imm) - { - operands[2] = GEN_INT (imm); - return "xxspltiw %x0,%2"; - } - } - } - if (TARGET_P9_VECTOR && xxspltib_constant_p (vec, mode, &num_insns, &xxspltib_value)) { @@ -26758,44 +26724,6 @@ prefixed_paddi_p (rtx_insn *insn) return (iform == INSN_FORM_PCREL_EXTERNAL || iform == INSN_FORM_PCREL_LOCAL); } -/* Whether an instruction is a prefixed XXSPLTI* instruction. This is called - from the prefixed attribute processing. */ - -bool -prefixed_xxsplti_p (rtx_insn *insn) -{ - rtx set = single_set (insn); - if (!set) - return false; - - rtx dest = SET_DEST (set); - rtx src = SET_SRC (set); - machine_mode mode = GET_MODE (dest); - - if (!REG_P (dest) && !SUBREG_P (dest)) - return false; - - if (GET_CODE (src) == UNSPEC) - { - int unspec = XINT (src, 1); - return (unspec == UNSPEC_XXSPLTIW - || unspec == UNSPEC_XXSPLTIDP - || unspec == UNSPEC_XXSPLTI32DX); - } - - rs6000_const vsx_const; - if (constant_to_bytes (src, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES)) - { - if (constant_generates_xxspltidp (&vsx_const)) - return true; - - if (constant_generates_xxspltiw (&vsx_const)) - return true; - } - - return false; -} - /* Whether the next instruction needs a 'p' prefix issued before the instruction is printed out. */ static bool prepend_p_to_next_insn; @@ -28659,464 +28587,6 @@ rs6000_output_addr_vec_elt (FILE *file, int value) fprintf (file, "\n"); } - -/* Copy an integer constant to the constant structure. */ - -static void -constant_integer_to_bytes (rtx op, - machine_mode mode, - size_t byte_num, - rs6000_const *info) -{ - unsigned HOST_WIDE_INT uvalue = UINTVAL (op); - unsigned bitsize = GET_MODE_BITSIZE (mode); - - for (int shift = bitsize - 8; shift >= 0; shift -= 8) - info->bytes[byte_num++] = (uvalue >> shift) & 0xff; -} - -/* Copy an floating point constant to the rs6000 constant structure. */ - -static void -constant_floating_point_to_bytes (rtx op, - machine_mode mode, - size_t byte_num, - rs6000_const *info) -{ - unsigned bitsize = GET_MODE_BITSIZE (mode); - unsigned num_words = bitsize / 32; - const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op); - long real_words[RS6000_CONST_MAX_WORDS]; - - /* Make sure we don't overflow the real_words array and that it is - filled completely. */ - gcc_assert (bitsize <= RS6000_CONST_MAX_BITS && (bitsize % 32) == 0); - - real_to_target (real_words, rtype, mode); - - /* Iterate over each 32-bit word in the floating point constant. The - real_to_target function puts out words in endian fashion. We need - to arrange so the words are written in big endian order. */ - for (unsigned num = 0; num < num_words; num++) - { - unsigned endian_num = (BYTES_BIG_ENDIAN - ? num - : num_words - 1 - num); - - unsigned uvalue = real_words[endian_num]; - for (int shift = 32 - 8; shift >= 0; shift -= 8) - info->bytes[byte_num++] = (uvalue >> shift) & 0xff; - } - - /* Mark that this constant involes floating point. */ - info->fp_constant_p = true; -} - -/* Convert an RTL constant OP with mode MODE to an internal structure INFO. - Possibly splat the constant to a larger size (SPLAT). - - Break out the constant out to bytes, half words, words, and double words. - Return true if we have successfully broken out a constant. - - We handle CONST_INT, CONST_DOUBLE, CONST_VECTOR, and VEC_DUPLICATE of - constants. */ - -bool -constant_to_bytes (rtx op, - machine_mode mode, - rs6000_const *info, - rs6000_const_splat splat) -{ - /* Initialize the constant structure. */ - memset ((void *)info, 0, sizeof (rs6000_const)); - - /* Assume plain integer constants are DImode. */ - if (mode == VOIDmode) - mode = CONST_INT_P (op) ? DImode : GET_MODE (op); - - if (mode == VOIDmode) - return false; - - unsigned size = GET_MODE_SIZE (mode); - - if (size > RS6000_CONST_MAX_BYTES) - return false; - - /* Set up the bits. */ - switch (GET_CODE (op)) - { - /* Integer constants, default to double word. */ - case CONST_INT: - { - constant_integer_to_bytes (op, mode, 0, info); - break; - } - - /* Floating point constants. */ - case CONST_DOUBLE: - { - /* Fail if the floating point constant is the wrong mode. */ - if (GET_MODE (op) != mode) - return false; - - /* SFmode stored as scalars are stored in DFmode format. */ - if (mode == SFmode) - { - mode = DFmode; - size = GET_MODE_SIZE (DFmode); - } - - constant_floating_point_to_bytes (op, mode, 0, info); - break; - } - - /* Vector constants, iterate over each element. On little endian - systems, we have to reverse the element numbers. */ - case CONST_VECTOR: - { - /* Fail if the vector constant is the wrong mode. */ - if (GET_MODE (op) != mode) - return false; - - machine_mode ele_mode = GET_MODE_INNER (mode); - size_t ele_size = GET_MODE_SIZE (ele_mode); - size_t nunits = GET_MODE_NUNITS (mode); - - for (size_t num = 0; num < nunits; num++) - { - rtx ele = CONST_VECTOR_ELT (op, num); - size_t byte_num = (BYTES_BIG_ENDIAN - ? num - : nunits - 1 - num) * ele_size; - - if (CONST_INT_P (ele)) - constant_integer_to_bytes (ele, ele_mode, byte_num, info); - else if (CONST_DOUBLE_P (ele)) - constant_floating_point_to_bytes (ele, ele_mode, byte_num, info); - else - return false; - } - - break; - } - - /* Treat VEC_DUPLICATE of a constant just like a vector constant. - Since we are duplicating the element, we don't have to worry about - endian issues. */ - case VEC_DUPLICATE: - { - /* Fail if the vector duplicate is the wrong mode. */ - if (GET_MODE (op) != mode) - return false; - - machine_mode ele_mode = GET_MODE_INNER (mode); - size_t ele_size = GET_MODE_SIZE (ele_mode); - rtx ele = XEXP (op, 0); - size_t nunits = GET_MODE_NUNITS (mode); - - if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele)) - return false; - - for (size_t num = 0; num < nunits; num++) - { - size_t byte_num = num * ele_size; - - if (CONST_INT_P (ele)) - constant_integer_to_bytes (ele, ele_mode, byte_num, info); - else - constant_floating_point_to_bytes (ele, ele_mode, byte_num, info); - } - - break; - } - - /* Any thing else, just return failure. */ - default: - return false; - } - - unsigned total_size = size; - - /* Possibly splat the constant to fill a vector size. */ - if (splat == RS6000_CONST_SPLAT_16_BYTES) - { - if (size < 16) - { - total_size = 16; - if ((total_size % size) != 0) - return false; - - for (size_t offset = size; offset < total_size; offset += size) - memcpy ((void *) &info->bytes[offset], - (void *) &info->bytes[0], - size); - } - } - - else if (splat != RS6000_CONST_NO_SPLAT) - return false; - - /* Remember total/original sizes. */ - info->total_size = total_size; - info->original_size = size; - - /* Determine if the bytes are all the same. */ - unsigned char first_byte = info->bytes[0]; - info->all_bytes_same = true; - for (size_t i = 1; i < total_size; i++) - if (first_byte != info->bytes[i]) - { - info->all_bytes_same = false; - break; - } - - /* Pack half words together & determine if all of the half words are the - same. */ - for (size_t i = 0; i < total_size; i += 2) - info->half_words[i / 2] = ((info->bytes[i] << 8) - | info->bytes[i + 1]); - - unsigned short first_hword = info->half_words[0]; - info->all_half_words_same = true; - for (size_t i = 1; i < total_size / 2; i++) - if (first_hword != info->half_words[i]) - { - info->all_half_words_same = false; - break; - } - - /* Pack words together & determine if all of the words are the same. */ - for (size_t i = 0; i < total_size; i += 4) - info->words[i / 4] = ((info->bytes[i] << 24) - | (info->bytes[i + 1] << 16) - | (info->bytes[i + 2] << 8) - | info->bytes[i + 3]); - - unsigned int first_word = info->words[0]; - info->all_words_same = true; - for (size_t i = 1; i < total_size / 4; i++) - if (first_word != info->words[i]) - { - info->all_words_same = false; - break; - } - - /* Pack double words together & determine if all of the double words are the - same. */ - for (size_t i = 0; i < total_size; i += 8) - { - unsigned HOST_WIDE_INT d_word = 0; - for (size_t j = 0; j < 8; j++) - d_word = (d_word << 8) | info->bytes[i + j]; - - info->double_words[i / 8] = d_word; - } - - unsigned HOST_WIDE_INT first_dword = info->double_words[0]; - info->all_double_words_same = true; - for (size_t i = 1; i < total_size / 8; i++) - if (first_dword != info->double_words[i]) - { - info->all_double_words_same = false; - break; - } - - return true; -} - -/* Determine if a vector constant can be loaded with XXSPLTIDP. Return zero if - the XXSPLTIDP instruction cannot be used. Otherwise return the immediate - value to be used with the XXSPLTIDP instruction. */ - -unsigned -constant_generates_xxspltidp (rs6000_const *vsx_const) -{ - if (!TARGET_SPLAT_FLOAT_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX) - return 0; - - /* Only recognize XXSPLTIDP for 16-byte vector constants (or 8-byte scalar - constants that have been splatted to 128-bits). */ - if (vsx_const->total_size != 16) - return 0; - - /* Make sure that the two 64-bit segments are the same. */ - if (!vsx_const->all_double_words_same) - return 0; - - /* If the bytes, half words, or words are all the same, don't use XXSPLTIDP. - Use a simpler instruction (XXSPLTIB, VSPLTISB, VSPLTISH, or VSPLTISW). */ - if (vsx_const->all_bytes_same - || vsx_const->all_half_words_same - || vsx_const->all_words_same) - return 0; - - unsigned HOST_WIDE_INT value = vsx_const->double_words[0]; - - /* Avoid values that look like DFmode NaN's, except for the normal NaN bit - pattern and the signalling NaN bit pattern. Recognize infinity and - negative infinity. */ - - /* Bit representation of DFmode normal quiet NaN. */ -#define RS6000_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000) - - /* Bit representation of DFmode normal signaling NaN. */ -#define RS6000_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000) - - /* Bit representation of DFmode positive infinity. */ -#define RS6000_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000) - - /* Bit representation of DFmode negative infinity. */ -#define RS6000_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000) - - if (value != RS6000_CONST_DF_NAN - && value != RS6000_CONST_DF_NANS - && value != RS6000_CONST_DF_INF - && value != RS6000_CONST_DF_NEG_INF) - { - /* The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for - the exponent, and 52 bits for the mantissa (not counting the hidden - bit used for normal numbers). NaN values have the exponent set to all - 1 bits, and the mantissa non-zero (mantissa == 0 is infinity). */ - - int df_exponent = (value >> 52) & 0x7ff; - unsigned HOST_WIDE_INT df_mantissa - = value & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U); - - if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */ - return 0; - - /* Avoid values that are DFmode subnormal values. Subnormal numbers have - the exponent all 0 bits, and the mantissa non-zero. If the value is - subnormal, then the hidden bit in the mantissa is not set. */ - if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */ - return 0; - } - - /* Change the representation to DFmode constant. */ - long df_words[2] = { vsx_const->words[0], vsx_const->words[1] }; - - /* real_from_target takes the target words in target order. */ - if (!BYTES_BIG_ENDIAN) - std::swap (df_words[0], df_words[1]); - - REAL_VALUE_TYPE rv_type; - real_from_target (&rv_type, df_words, DFmode); - - const REAL_VALUE_TYPE *rv = &rv_type; - - /* Validate that the number can be stored as a SFmode value. */ - if (!exact_real_truncate (SFmode, rv)) - return 0; - - /* Validate that the number is not a SFmode subnormal value (exponent is 0, - mantissa field is non-zero) which is undefined for the XXSPLTIDP - instruction. */ - long sf_value; - real_to_target (&sf_value, rv, SFmode); - - /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent, - and 23 bits for the mantissa. Subnormal numbers have the exponent all - 0 bits, and the mantissa non-zero. */ - long sf_exponent = (sf_value >> 23) & 0xFF; - long sf_mantissa = sf_value & 0x7FFFFF; - - if (sf_exponent == 0 && sf_mantissa != 0) - return 0; - - /* Return the immediate to be used. */ - return sf_value; -} - -/* Determine if a vector constant can be loaded with XXSPLTIW. Return zero if - the XXSPLTIW instruction cannot be used. Otherwise return the immediate - value to be used with the XXSPLTIW instruction. */ - -unsigned -constant_generates_xxspltiw (rs6000_const *vsx_const) -{ - if (!TARGET_SPLAT_WORD_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX) - return 0; - - if (!vsx_const->all_words_same) - return 0; - - /* If we can use XXSPLTIB, don't generate XXSPLTIW. */ - if (vsx_const->all_bytes_same) - return 0; - - /* See if we can use VSPLTISH or VSPLTISW. */ - if (vsx_const->all_half_words_same) - { - unsigned short h_word = vsx_const->half_words[0]; - short sign_h_word = ((h_word & 0xffff) ^ 0x8000) - 0x8000; - if (EASY_VECTOR_15 (sign_h_word)) - return 0; - } - - unsigned int word = vsx_const->words[0]; - int sign_word = ((word & 0xffffffff) ^ 0x80000000) - 0x80000000; - if (EASY_VECTOR_15 (sign_word)) - return 0; - - return vsx_const->words[0]; -} - -/* Determine if an IEEE 128-bit constant can be loaded with LXVKQ. Return zero - if the LXVKQ instruction cannot be used. Otherwise return the immediate - value to be used with the LXVKQ instruction. */ - -unsigned -constant_generates_lxvkq (rs6000_const *vsx_const) -{ - /* Is the instruction supported with power10 code generation, IEEE 128-bit - floating point hardware and VSX registers are available. */ - if (!TARGET_IEEE128_CONSTANT || !TARGET_FLOAT128_HW || !TARGET_POWER10 - || !TARGET_VSX) - return 0; - - /* Only recognize LXVKQ for 16-byte (4 word) vector constants. */ - unsigned total_size = vsx_const->total_size; - if (total_size != 16) - return 0; - - /* Verify that all of the bottom 3 words in the constants loaded by the - LXVKQ instruction are zero. */ - if (vsx_const->words[1] != 0 - || vsx_const->words[2] != 0 - || vsx_const->words[3] != 0) - return 0; - - /* See if we have a match. */ - switch (vsx_const->words[0]) - { - case 0x3FFF0000U: return 1; /* IEEE 128-bit +1.0. */ - case 0x40000000U: return 2; /* IEEE 128-bit +2.0. */ - case 0x40008000U: return 3; /* IEEE 128-bit +3.0. */ - case 0x40010000U: return 4; /* IEEE 128-bit +4.0. */ - case 0x40014000U: return 5; /* IEEE 128-bit +5.0. */ - case 0x40018000U: return 6; /* IEEE 128-bit +6.0. */ - case 0x4001C000U: return 7; /* IEEE 128-bit +7.0. */ - case 0x7FFF0000U: return 8; /* IEEE 128-bit +Infinity. */ - case 0x7FFF8000U: return 9; /* IEEE 128-bit quiet NaN. */ - case 0x80000000U: return 16; /* IEEE 128-bit -0.0. */ - case 0xBFFF0000U: return 17; /* IEEE 128-bit -1.0. */ - case 0xC0000000U: return 18; /* IEEE 128-bit -2.0. */ - case 0xC0008000U: return 19; /* IEEE 128-bit -3.0. */ - case 0xC0010000U: return 20; /* IEEE 128-bit -4.0. */ - case 0xC0014000U: return 21; /* IEEE 128-bit -5.0. */ - case 0xC0018000U: return 22; /* IEEE 128-bit -6.0. */ - case 0xC001C000U: return 23; /* IEEE 128-bit -7.0. */ - case 0xFFFF0000U: return 24; /* IEEE 128-bit -Infinity. */ - - /* anything else cannot be loaded. */ - default: - break; - } - - return 0; -} - - struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rs6000.h" diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 3c94e547939..6bec2bddbde 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -156,8 +156,6 @@ UNSPEC_PEXTD UNSPEC_HASHST UNSPEC_HASHCHK - UNSPEC_XXSPLTIDP_CONST - UNSPEC_XXSPLTIW_CONST ]) ;; @@ -316,11 +314,6 @@ (eq_attr "type" "integer,add") (if_then_else (match_test "prefixed_paddi_p (insn)") - (const_string "yes") - (const_string "no")) - - (eq_attr "type" "vecperm") - (if_then_else (match_test "prefixed_xxsplti_p (insn)") (const_string "yes") (const_string "no"))] @@ -7766,17 +7759,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT MF NOP XXSPLTIDP +;; MR MT MF NOP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h, wa") + !r, *c*l, !r, *h") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0, eP"))] + r, r, *h, 0"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7798,16 +7791,15 @@ mr %0,%1 mt%0 %1 mf%1 %0 - nop - #" + nop" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *, vecperm") + *, mtjmpr, mfjmpr, *") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *, p10")]) + *, *, *, *")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -8067,18 +8059,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR XXSPLTIDP +;; LWZ STW MR (define_insn "*mov_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, - Y, r, !r, wa") + Y, r, !r") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , - r, Y, r, eP"))] + r, Y, r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8095,21 +8087,20 @@ # # # - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two, vecperm") + store, load, two") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8, *") + 8, 8, 8") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *, p10")]) + *, *, *")]) ;; STW LWZ MR G-const H-const F-const @@ -8136,19 +8127,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFVSRD MTVSRD XXSPLTIDP +;; NOP MFVSRD MTVSRD (define_insn "*mov_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, , Z, , , !r, YZ, r, !r, *c*l, !r, - *h, r, , wa") + *h, r, ") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , Z, , , , , r, YZ, r, r, *h, - 0, , r, eP"))] + 0, , r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode))" @@ -8170,19 +8161,18 @@ mf%1 %0 nop mfvsrd %0,%x1 - mtvsrd %x0,%1 - #" + mtvsrd %x0,%1" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr, vecperm") + *, mfvsr, mtvsr") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, *, *, *, *, *, - *, p8v, p8v, p10")]) + *, p8v, p8v")]) ;; STD LD MR MT MF G-const ;; H-const F-const Special @@ -8216,62 +8206,6 @@ (set_attr "length" "*, *, *, *, *, 8, 12, 16, *")]) - -;; Split the VSX prefixed instruction to support SFmode and DFmode scalar -;; constants that look like DFmode floating point values where both elements -;; are the same. The constant has to be expressible as a SFmode constant that -;; is not a SFmode denormal value. -;; -;; We don't need splitters for the 128-bit types, since the function -;; rs6000_output_move_128bit handles the generation of XXSPLTIDP. -(define_insn "xxspltidp__internal" - [(set (match_operand:SFDF 0 "register_operand" "=wa") - (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] - UNSPEC_XXSPLTIDP_CONST))] - "TARGET_POWER10" - "xxspltidp %x0,%1" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - -(define_insn "xxspltiw__internal" - [(set (match_operand:SFDF 0 "register_operand" "=wa") - (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] - UNSPEC_XXSPLTIW_CONST))] - "TARGET_POWER10" - "xxspltiw %x0,%1" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - -(define_split - [(set (match_operand:SFDF 0 "vsx_register_operand") - (match_operand:SFDF 1 "vsx_prefixed_constant"))] - "TARGET_POWER10" - [(pc)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - rs6000_const vsx_const; - - if (!constant_to_bytes (src, mode, &vsx_const, RS6000_CONST_SPLAT_16_BYTES)) - gcc_unreachable (); - - unsigned imm = constant_generates_xxspltidp (&vsx_const); - if (imm) - { - emit_insn (gen_xxspltidp__internal (dest, GEN_INT (imm))); - DONE; - } - - imm = constant_generates_xxspltiw (&vsx_const); - if (imm) - { - emit_insn (gen_xxspltiw__internal (dest, GEN_INT (imm))); - DONE; - } - - else - gcc_unreachable (); -}) (define_expand "mov" [(set (match_operand:FMOVE128 0 "general_operand") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 3ddac80289c..9d7878f144a 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -640,18 +640,6 @@ mprivileged Target Var(rs6000_privileged) Init(0) Generate code that will run in privileged state. -msplat-float-constant -Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save -Generate (do not generate) code that uses the XXSPLTIDP instruction. - -msplat-word-constant -Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save -Generate (do not generate) code that uses the XXSPLTIW instruction. - -mieee128-constant -Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save -Generate (do not generate) code that uses the LXVKQ instruction. - -param=rs6000-density-pct-threshold= Target Undocumented Joined UInteger Var(rs6000_density_pct_threshold) Init(85) IntegerRange(0, 100) Param When costing for loop vectorization, we probably need to penalize the loop body diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md index ce8402101ef..bf033e31c1c 100644 --- a/gcc/config/rs6000/vsx.md +++ b/gcc/config/rs6000/vsx.md @@ -1192,19 +1192,16 @@ ;; VSX store VSX load VSX move VSX->GPR GPR->VSX LQ (GPR) ;; STQ (GPR) GPR load GPR store GPR move XXSPLTIB VSPLTISW -;; XXLSPLTI* LXVKQ ;; VSX 0/-1 VMX const GPR const LVX (VMX) STVX (VMX) (define_insn "vsx_mov_64bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, r, we, ?wQ, ?&r, ??r, ??Y, , wa, v, - wa, wa, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, we, r, r, wQ, Y, r, r, wE, jwM, - eP, eQ, ?jwM, W, , v, wZ"))] "TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) @@ -1216,47 +1213,36 @@ [(set_attr "type" "vecstore, vecload, vecsimple, mtvsr, mfvsr, load, store, load, store, *, vecsimple, vecsimple, - vecperm, vecperm, vecsimple, *, *, vecstore, vecload") (set_attr "num_insns" "*, *, *, 2, *, 2, 2, 2, 2, 2, *, *, - *, *, *, 5, 2, *, *") (set_attr "max_prefixed_insns" "*, *, *, *, *, 2, 2, 2, 2, 2, *, *, - *, *, *, *, *, *, *") (set_attr "length" "*, *, *, 8, *, 8, 8, 8, 8, 8, *, *, - *, *, *, 20, 8, *, *") (set_attr "isa" ", , , *, *, *, *, *, *, *, p9v, *, - p10, p10, , *, *, *, *")]) ;; VSX store VSX load VSX move GPR load GPR store GPR move -;; XXSPLTIB VSPLTISW VSX 0/-1 -;; XXSPLTI* LXVKQ -;; VMX const GPR const +;; XXSPLTIB VSPLTISW VSX 0/-1 VMX const GPR const ;; LVX (VMX) STVX (VMX) (define_insn "*vsx_mov_32bit" [(set (match_operand:VSX_M 0 "nonimmediate_operand" "=ZwO, wa, wa, ??r, ??Y, , - wa, v, ?wa, - wa, wa, - v, , + wa, v, ?wa, v, , wZ, v") (match_operand:VSX_M 1 "input_operand" "wa, ZwO, wa, Y, r, r, - wE, jwM, ?jwM, - eP, eQ, - W, , + wE, jwM, ?jwM, W, , v, wZ"))] "!TARGET_POWERPC64 && VECTOR_MEM_VSX_P (mode) @@ -1267,21 +1253,15 @@ } [(set_attr "type" "vecstore, vecload, vecsimple, load, store, *, - vecsimple, vecsimple, vecsimple, - vecperm, vecperm, - *, *, + vecsimple, vecsimple, vecsimple, *, *, vecstore, vecload") (set_attr "length" "*, *, *, 16, 16, 16, - *, *, *, - *, *, - 20, 16, + *, *, *, 20, 16, *, *") (set_attr "isa" ", , , *, *, *, - p9v, *, , - p10, p10, - *, *, + p9v, *, , *, *, *, *")]) ;; Explicit load/store expanders for the builtin functions diff --git a/gcc/doc/md.texi b/gcc/doc/md.texi index 41a568b7d4e..41f1850bf6e 100644 --- a/gcc/doc/md.texi +++ b/gcc/doc/md.texi @@ -3336,14 +3336,6 @@ A constant whose negation is a signed 16-bit constant. @item eI A signed 34-bit integer constant if prefixed instructions are supported. -@item eP -A scalar floating point constant or a vector constant that can be -loaded with one prefixed instruction to a VSX register. - -@item eQ -An IEEE 128-bit constant that can be loaded into a VSX register with a -single instruction. - @ifset INTERNALS @item G A floating point constant that can be loaded into a register with one diff --git a/gcc/testsuite/gcc.target/powerpc/float128-constant.c b/gcc/testsuite/gcc.target/powerpc/float128-constant.c deleted file mode 100644 index e3286a786a5..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/float128-constant.c +++ /dev/null @@ -1,160 +0,0 @@ -/* { dg-require-effective-target ppc_float128_hw } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -/* Test whether the LXVKQ instruction is generated to load special IEEE 128-bit - constants. */ - -_Float128 -return_0 (void) -{ - return 0.0f128; /* XXSPLTIB 34,0. */ -} - -_Float128 -return_1 (void) -{ - return 1.0f128; /* LXVKQ 34,1. */ -} - -_Float128 -return_2 (void) -{ - return 2.0f128; /* LXVKQ 34,2. */ -} - -_Float128 -return_3 (void) -{ - return 3.0f128; /* LXVKQ 34,3. */ -} - -_Float128 -return_4 (void) -{ - return 4.0f128; /* LXVKQ 34,4. */ -} - -_Float128 -return_5 (void) -{ - return 5.0f128; /* LXVKQ 34,5. */ -} - -_Float128 -return_6 (void) -{ - return 6.0f128; /* LXVKQ 34,6. */ -} - -_Float128 -return_7 (void) -{ - return 7.0f128; /* LXVKQ 34,7. */ -} - -_Float128 -return_m0 (void) -{ - return -0.0f128; /* LXVKQ 34,16. */ -} - -_Float128 -return_m1 (void) -{ - return -1.0f128; /* LXVKQ 34,17. */ -} - -_Float128 -return_m2 (void) -{ - return -2.0f128; /* LXVKQ 34,18. */ -} - -_Float128 -return_m3 (void) -{ - return -3.0f128; /* LXVKQ 34,19. */ -} - -_Float128 -return_m4 (void) -{ - return -4.0f128; /* LXVKQ 34,20. */ -} - -_Float128 -return_m5 (void) -{ - return -5.0f128; /* LXVKQ 34,21. */ -} - -_Float128 -return_m6 (void) -{ - return -6.0f128; /* LXVKQ 34,22. */ -} - -_Float128 -return_m7 (void) -{ - return -7.0f128; /* LXVKQ 34,23. */ -} - -_Float128 -return_inf (void) -{ - return __builtin_inff128 (); /* LXVKQ 34,8. */ -} - -_Float128 -return_minf (void) -{ - return - __builtin_inff128 (); /* LXVKQ 34,24. */ -} - -_Float128 -return_nan (void) -{ - return __builtin_nanf128 (""); /* LXVKQ 34,9. */ -} - -/* Note, the following NaNs should not generate a LXVKQ instruction. */ -_Float128 -return_mnan (void) -{ - return - __builtin_nanf128 (""); /* PLXV 34,... */ -} - -_Float128 -return_nan2 (void) -{ - return __builtin_nanf128 ("1"); /* PLXV 34,... */ -} - -_Float128 -return_nans (void) -{ - return __builtin_nansf128 (""); /* PLXV 34,... */ -} - -vector long long -return_longlong_neg_0 (void) -{ - /* This vector is the same pattern as -0.0F128. */ -#if __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ -#define FIRST 0x8000000000000000 -#define SECOND 0x0000000000000000 - -#else -#define FIRST 0x0000000000000000 -#define SECOND 0x8000000000000000 -#endif - - return (vector long long) { FIRST, SECOND }; /* LXVKQ 34,16. */ -} - -/* { dg-final { scan-assembler-times {\mlxvkq\M} 19 } } */ -/* { dg-final { scan-assembler-times {\mplxv\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mxxspltib\M} 1 } } */ - diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c index dcb30e1d886..bd1502bb30a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c @@ -24,12 +24,11 @@ vector signed long long splats4(void) return (vector signed long long) vec_sl(mzero, mzero); } -/* Codegen will consist of splat and shift instructions for most types. If - folding is enabled, the vec_sl tests using vector long long type will - generate a lvx instead of a vspltisw+vsld pair. On power10, it will - generate a xxspltidp instruction instead of the lvx. */ +/* Codegen will consist of splat and shift instructions for most types. + If folding is enabled, the vec_sl tests using vector long long type will + generate a lvx instead of a vspltisw+vsld pair. */ /* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */ /* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */ -/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c deleted file mode 100644 index 8f6e176f9af..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c +++ /dev/null @@ -1,60 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include - -/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -double -scalar_double_0 (void) -{ - return 0.0; /* XXSPLTIB or XXLXOR. */ -} - -double -scalar_double_1 (void) -{ - return 1.0; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -double -scalar_double_m0 (void) -{ - return -0.0; /* XXSPLTIDP. */ -} - -double -scalar_double_nan (void) -{ - return __builtin_nan (""); /* XXSPLTIDP. */ -} - -double -scalar_double_inf (void) -{ - return __builtin_inf (); /* XXSPLTIDP. */ -} - -double -scalar_double_m_inf (void) /* XXSPLTIDP. */ -{ - return - __builtin_inf (); -} -#endif - -double -scalar_double_pi (void) -{ - return M_PI; /* PLFD. */ -} - -double -scalar_double_denorm (void) -{ - return 0x1p-149f; /* PLFD. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c deleted file mode 100644 index 72504bdfbbd..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c +++ /dev/null @@ -1,60 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include - -/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -float -scalar_float_0 (void) -{ - return 0.0f; /* XXSPLTIB or XXLXOR. */ -} - -float -scalar_float_1 (void) -{ - return 1.0f; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -float -scalar_float_m0 (void) -{ - return -0.0f; /* XXSPLTIDP. */ -} - -float -scalar_float_nan (void) -{ - return __builtin_nanf (""); /* XXSPLTIDP. */ -} - -float -scalar_float_inf (void) -{ - return __builtin_inff (); /* XXSPLTIDP. */ -} - -float -scalar_float_m_inf (void) /* XXSPLTIDP. */ -{ - return - __builtin_inff (); -} -#endif - -float -scalar_float_pi (void) -{ - return (float)M_PI; /* XXSPLTIDP. */ -} - -float -scalar_float_denorm (void) -{ - return 0x1p-149f; /* PLFS. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c deleted file mode 100644 index 27764ddbc83..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v16qi.c +++ /dev/null @@ -1,27 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include - -/* Test whether XXSPLTIW is generated for V16HI vector constants where the - first 4 elements are the same as the next 4 elements, etc. */ - -vector unsigned char -v16qi_const_1 (void) -{ - return (vector unsigned char) { 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, }; /* VSLTPISB. */ -} - -vector unsigned char -v16qi_const_2 (void) -{ - return (vector unsigned char) { 1, 2, 3, 4, 1, 2, 3, 4, - 1, 2, 3, 4, 1, 2, 3, 4, }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 1 } } */ -/* { dg-final { scan-assembler-times {\mvspltisb\M|\mxxspltib\M} 1 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c deleted file mode 100644 index 82ffc86f8aa..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c +++ /dev/null @@ -1,64 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include - -/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -vector double -v2df_double_0 (void) -{ - return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */ -} - -vector double -v2df_double_1 (void) -{ - return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -vector double -v2df_double_m0 (void) -{ - return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_nan (void) -{ - return (vector double) { __builtin_nan (""), - __builtin_nan ("") }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_inf (void) -{ - return (vector double) { __builtin_inf (), - __builtin_inf () }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_m_inf (void) -{ - return (vector double) { - __builtin_inf (), - - __builtin_inf () }; /* XXSPLTIDP. */ -} -#endif - -vector double -v2df_double_pi (void) -{ - return (vector double) { M_PI, M_PI }; /* PLVX. */ -} - -vector double -v2df_double_denorm (void) -{ - return (vector double) { (double)0x1p-149f, - (double)0x1p-149f }; /* PLVX. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c deleted file mode 100644 index 4d44f943d26..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c +++ /dev/null @@ -1,50 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -/* Test generating V2DImode constants that have the same bit pattern as - V2DFmode constants that can be loaded with the XXSPLTIDP instruction with - the ISA 3.1 (power10). */ - -vector long long -vector_0 (void) -{ - /* XXSPLTIB or XXLXOR. */ - return (vector long long) { 0LL, 0LL }; -} - -vector long long -vector_1 (void) -{ - /* XXSPLTIB and VEXTSB2D. */ - return (vector long long) { 1LL, 1LL }; -} - -/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated - with XXSPLTISDP. */ -vector long long -vector_float_neg_0 (void) -{ - /* XXSPLTIDP. */ - return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL }; -} - -/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with - XXSPLTISDP. */ -vector long long -vector_float_1_0 (void) -{ - /* XXSPLTIDP. */ - return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL }; -} - -/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated - with XXSPLTIDP. */ -vector long long -scalar_pi (void) -{ - /* PLXV. */ - return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL }; -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c deleted file mode 100644 index 1f0475cf47a..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4sf.c +++ /dev/null @@ -1,67 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include - -/* Test whether XXSPLTIW is generated for V4SF vector constants. */ - -vector float -v4sf_const_1 (void) -{ - return (vector float) { 1.0f, 1.0f, 1.0f, 1.0f }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_nan (void) -{ - return (vector float) { __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf (""), - __builtin_nanf ("") }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_inf (void) -{ - return (vector float) { __builtin_inff (), - __builtin_inff (), - __builtin_inff (), - __builtin_inff () }; /* XXSPLTIW. */ -} - -vector float -v4sf_const_m0 (void) -{ - return (vector float) { -0.0f, -0.0f, -0.0f, -0.0f }; /* XXSPLTIB/VSLW. */ -} - -vector float -v4sf_splats_1 (void) -{ - return vec_splats (1.0f); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_nan (void) -{ - return vec_splats (__builtin_nanf ("")); /* XXSPLTIW. */ -} - -vector float -v4sf_splats_inf (void) -{ - return vec_splats (__builtin_inff ()); /* XXSPLTIW. */ -} - -vector float -v8hi_splats_m0 (void) -{ - return vec_splats (-0.0f); /* XXSPLTIB/VSLW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 6 } } */ -/* { dg-final { scan-assembler-times {\mxxspltib\M} 2 } } */ -/* { dg-final { scan-assembler-times {\mvslw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c deleted file mode 100644 index 02d0c6d66a2..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v4si.c +++ /dev/null @@ -1,51 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include - -/* Test whether XXSPLTIW is generated for V4SI vector constants. We make sure - the power9 support (XXSPLTIB/VEXTSB2W) is not done. */ - -vector int -v4si_const_1 (void) -{ - return (vector int) { 1, 1, 1, 1 }; /* VSLTPISW. */ -} - -vector int -v4si_const_126 (void) -{ - return (vector int) { 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector int -v4si_const_1023 (void) -{ - return (vector int) { 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector int -v4si_splats_1 (void) -{ - return vec_splats (1); /* VSLTPISW. */ -} - -vector int -v4si_splats_126 (void) -{ - return vec_splats (126); /* XXSPLTIW. */ -} - -vector int -v8hi_splats_1023 (void) -{ - return vec_splats (1023); /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 4 } } */ -/* { dg-final { scan-assembler-times {\mvspltisw\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvextsb2w\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c deleted file mode 100644 index 59418d3bb0a..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v8hi.c +++ /dev/null @@ -1,62 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include - -/* Test whether XXSPLTIW is generated for V8HI vector constants. We make sure - the power9 support (XXSPLTIB/VUPKLSB) is not done. */ - -vector short -v8hi_const_1 (void) -{ - return (vector short) { 1, 1, 1, 1, 1, 1, 1, 1 }; /* VSLTPISH. */ -} - -vector short -v8hi_const_126 (void) -{ - return (vector short) { 126, 126, 126, 126, - 126, 126, 126, 126 }; /* XXSPLTIW. */ -} - -vector short -v8hi_const_1023 (void) -{ - return (vector short) { 1023, 1023, 1023, 1023, - 1023, 1023, 1023, 1023 }; /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1 (void) -{ - return vec_splats ((short)1); /* VSLTPISH. */ -} - -vector short -v8hi_splats_126 (void) -{ - return vec_splats ((short)126); /* XXSPLTIW. */ -} - -vector short -v8hi_splats_1023 (void) -{ - return vec_splats ((short)1023); /* XXSPLTIW. */ -} - -/* Test that we can optimiza V8HI where all of the even elements are the same - and all of the odd elements are the same. */ -vector short -v8hi_const_1023_1000 (void) -{ - return (vector short) { 1023, 1000, 1023, 1000, - 1023, 1000, 1023, 1000 }; /* XXSPLTIW. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 5 } } */ -/* { dg-final { scan-assembler-times {\mvspltish\M} 2 } } */ -/* { dg-final { scan-assembler-not {\mxxspltib\M} } } */ -/* { dg-final { scan-assembler-not {\mvupklsb\M} } } */ -/* { dg-final { scan-assembler-not {\mlxvx?\M} } } */ -/* { dg-final { scan-assembler-not {\mplxv\M} } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c index 6c01666b625..a135279b1d7 100644 --- a/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c +++ b/gcc/testsuite/gcc.target/powerpc/vec-splati-runnable.c @@ -149,8 +149,8 @@ main (int argc, char *argv []) return 0; } -/* { dg-final { scan-assembler-times {\mxxspltiw\M} 3 } } */ -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 3 } } */ +/* { dg-final { scan-assembler-times {\mxxspltiw\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */ /* { dg-final { scan-assembler-times {\mxxsplti32dx\M} 3 } } */