[gcc r12-4656] RISC-V: Cost model for zbb extension.

[gcc r12-4656] RISC-V: Cost model for zbb extension.

[Kito Cheng]

https://gcc.gnu.org/g:3329d892eb603fbe4e7c393f19d35739fe400a22

commit r12-4656-g3329d892eb603fbe4e7c393f19d35739fe400a22
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Thu Sep 16 22:19:44 2021 +0800

    RISC-V: Cost model for zbb extension.
    
    2021-10-25  Kito Cheng  <kito.cheng@sifive.com>
    
    gcc/ChangeLog:
    
            * config/riscv/riscv.c (riscv_extend_cost): Handle cost model
            for zbb extension.
            (riscv_rtx_costs): Ditto.

Diff:
---
 gcc/config/riscv/riscv.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c
index dec31c0ca6f..cb93e3fb88a 100644
--- a/gcc/config/riscv/riscv.c
+++ b/gcc/config/riscv/riscv.c
@@ -1707,6 +1707,16 @@ riscv_extend_cost (rtx op, bool unsigned_p)
   if (TARGET_ZBA && TARGET_64BIT && unsigned_p && GET_MODE (op) == SImode)
     return COSTS_N_INSNS (1);
 
+  /* ZBB provide zext.h, sext.b and sext.h.  */
+  if (TARGET_ZBB)
+    {
+      if (!unsigned_p && GET_MODE (op) == QImode)
+	return COSTS_N_INSNS (1);
+
+      if (GET_MODE (op) == HImode)
+	return COSTS_N_INSNS (1);
+    }
+
   if (!unsigned_p && GET_MODE (op) == SImode)
     /* We can use SEXT.W.  */
     return COSTS_N_INSNS (1);
@@ -1797,6 +1807,13 @@ riscv_rtx_costs (rtx x, machine_mode mode, int outer_code, int opno ATTRIBUTE_UN
       gcc_fallthrough ();
     case IOR:
     case XOR:
+      /* orn, andn and xorn pattern for zbb.  */
+      if (TARGET_ZBB
+	  && GET_CODE (XEXP (x, 0)) == NOT)
+	{
+	  *total = riscv_binary_cost (x, 1, 2);
+	  return true;
+	}
       /* Double-word operations use two single-word operations.  */
       *total = riscv_binary_cost (x, 1, 2);
       return false;