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From: Kito Cheng <kito@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-4657] RISC-V: Use li and rori to load constants. Date: Mon, 25 Oct 2021 09:11:56 +0000 (GMT) [thread overview] Message-ID: <20211025091156.2E186385843E@sourceware.org> (raw) https://gcc.gnu.org/g:26d2818bb73a09622f87df53d6280d18b229bcbc commit r12-4657-g26d2818bb73a09622f87df53d6280d18b229bcbc Author: Jim Wilson <jimw@sifive.com> Date: Sat Oct 31 11:41:19 2020 -0700 RISC-V: Use li and rori to load constants. gcc/ChangeLog: * config/riscv/riscv.c (riscv_build_integer_1): Build integer with rotate. gcc/testsuite/ChangeLog: * gcc.target/riscv/zbb-li-rotr.c: New. Diff: --- gcc/config/riscv/riscv.c | 41 ++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c | 35 ++++++++++++++++++++++++ 2 files changed, 76 insertions(+) diff --git a/gcc/config/riscv/riscv.c b/gcc/config/riscv/riscv.c index cb93e3fb88a..3ed34f234e5 100644 --- a/gcc/config/riscv/riscv.c +++ b/gcc/config/riscv/riscv.c @@ -462,6 +462,47 @@ riscv_build_integer_1 (struct riscv_integer_op codes[RISCV_MAX_INTEGER_OPS], } } + if (cost > 2 && TARGET_64BIT && TARGET_ZBB) + { + int leading_ones = clz_hwi (~value); + int trailing_ones = ctz_hwi (~value); + + /* If all bits are one except a few that are zero, and the zero bits + are within a range of 11 bits, and at least one of the upper 32-bits + is a zero, then we can generate a constant by loading a small + negative constant and rotating. */ + if (leading_ones < 32 + && ((64 - leading_ones - trailing_ones) < 12)) + { + codes[0].code = UNKNOWN; + /* The sign-bit might be zero, so just rotate to be safe. */ + codes[0].value = (((unsigned HOST_WIDE_INT) value >> trailing_ones) + | (value << (64 - trailing_ones))); + codes[1].code = ROTATERT; + codes[1].value = 64 - trailing_ones; + cost = 2; + } + /* Handle the case where the 11 bit range of zero bits wraps around. */ + else + { + int upper_trailing_ones = ctz_hwi (~value >> 32); + int lower_leading_ones = clz_hwi (~value << 32); + + if (upper_trailing_ones < 32 && lower_leading_ones < 32 + && ((64 - upper_trailing_ones - lower_leading_ones) < 12)) + { + codes[0].code = UNKNOWN; + /* The sign-bit might be zero, so just rotate to be safe. */ + codes[0].value = ((value << (32 - upper_trailing_ones)) + | ((unsigned HOST_WIDE_INT) value + >> (32 + upper_trailing_ones))); + codes[1].code = ROTATERT; + codes[1].value = 32 - upper_trailing_ones; + cost = 2; + } + } + } + gcc_assert (cost <= RISCV_MAX_INTEGER_OPS); return cost; } diff --git a/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c new file mode 100644 index 00000000000..03254ed9150 --- /dev/null +++ b/gcc/testsuite/gcc.target/riscv/zbb-li-rotr.c @@ -0,0 +1,35 @@ +/* { dg-do compile } */ +/* { dg-options "-march=rv64gc_zbb -mabi=lp64 -O2" } */ + +long +li_rori (void) +{ + return 0xffff77ffffffffffL; +} + +long +li_rori_2 (void) +{ + return 0x77ffffffffffffffL; +} + +long +li_rori_3 (void) +{ + return 0xfffffffeefffffffL; +} + +long +li_rori_4 (void) +{ + return 0x5ffffffffffffff5L; +} + +long +li_rori_5 (void) +{ + return 0xaffffffffffffffaL; +} + + +/* { dg-final { scan-assembler-times "rori\t" 5 } } */
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