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* [gcc r12-4758] rs6000: Fold xxsel to vsel since they have same semantics
@ 2021-10-28 3:18 Xiong Hu Luo
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From: Xiong Hu Luo @ 2021-10-28 3:18 UTC (permalink / raw)
To: gcc-cvs
https://gcc.gnu.org/g:5f9ef1339e9d0d709af6a70b60e584bf7decd761
commit r12-4758-g5f9ef1339e9d0d709af6a70b60e584bf7decd761
Author: Xionghu Luo <luoxhu@linux.ibm.com>
Date: Wed Oct 27 21:22:39 2021 -0500
rs6000: Fold xxsel to vsel since they have same semantics
Fold xxsel to vsel like xxperm/vperm to avoid duplicate code.
gcc/ChangeLog:
2021-10-28 Xionghu Luo <luoxhu@linux.ibm.com>
PR target/94613
* config/rs6000/altivec.md: Add vsx register constraints.
* config/rs6000/vsx.md (vsx_xxsel<mode>): Delete.
(vsx_xxsel<mode>2): Likewise.
(vsx_xxsel<mode>3): Likewise.
(vsx_xxsel<mode>4): Likewise.
gcc/testsuite/ChangeLog:
2021-10-28 Xionghu Luo <luoxhu@linux.ibm.com>
* gcc.target/powerpc/builtins-1.c: Adjust.
Diff:
---
gcc/config/rs6000/altivec.md | 60 ++++++++++++++++-----------
gcc/config/rs6000/vsx.md | 57 -------------------------
gcc/testsuite/gcc.target/powerpc/builtins-1.c | 2 +-
3 files changed, 37 insertions(+), 82 deletions(-)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index 158b3a708a3..a057218aa28 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -682,56 +682,68 @@
[(set_attr "type" "veccmp")])
(define_insn "altivec_vsel<mode>"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (not:VM (match_operand:VM 3 "altivec_register_operand" "v"))
- (match_operand:VM 1 "altivec_register_operand" "v"))
+ (not:VM (match_operand:VM 3 "register_operand" "wa,v"))
+ (match_operand:VM 1 "register_operand" "wa,v"))
(and:VM
(match_dup 3)
- (match_operand:VM 2 "altivec_register_operand" "v"))))]
+ (match_operand:VM 2 "register_operand" "wa,v"))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%1,%2,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x1,%x2,%x3
+ vsel %0,%1,%2,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
(define_insn "altivec_vsel<mode>2"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (not:VM (match_operand:VM 3 "altivec_register_operand" "v"))
- (match_operand:VM 1 "altivec_register_operand" "v"))
+ (not:VM (match_operand:VM 3 "register_operand" "wa,v"))
+ (match_operand:VM 1 "register_operand" "wa,v"))
(and:VM
- (match_operand:VM 2 "altivec_register_operand" "v")
+ (match_operand:VM 2 "register_operand" "wa,v")
(match_dup 3))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%1,%2,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x1,%x2,%x3
+ vsel %0,%1,%2,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
(define_insn "altivec_vsel<mode>3"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (match_operand:VM 3 "altivec_register_operand" "v")
- (match_operand:VM 1 "altivec_register_operand" "v"))
+ (match_operand:VM 3 "register_operand" "wa,v")
+ (match_operand:VM 1 "register_operand" "wa,v"))
(and:VM
(not:VM (match_dup 3))
- (match_operand:VM 2 "altivec_register_operand" "v"))))]
+ (match_operand:VM 2 "register_operand" "wa,v"))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%2,%1,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x2,%x1,%x3
+ vsel %0,%2,%1,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
(define_insn "altivec_vsel<mode>4"
- [(set (match_operand:VM 0 "altivec_register_operand" "=v")
+ [(set (match_operand:VM 0 "register_operand" "=wa,v")
(ior:VM
(and:VM
- (match_operand:VM 1 "altivec_register_operand" "v")
- (match_operand:VM 3 "altivec_register_operand" "v"))
+ (match_operand:VM 1 "register_operand" "wa,v")
+ (match_operand:VM 3 "register_operand" "wa,v"))
(and:VM
(not:VM (match_dup 3))
- (match_operand:VM 2 "altivec_register_operand" "v"))))]
+ (match_operand:VM 2 "register_operand" "wa,v"))))]
"VECTOR_MEM_ALTIVEC_OR_VSX_P (<MODE>mode)"
- "vsel %0,%2,%1,%3"
- [(set_attr "type" "vecmove")])
+ "@
+ xxsel %x0,%x2,%x1,%x3
+ vsel %0,%2,%1,%3"
+ [(set_attr "type" "vecmove")
+ (set_attr "isa" "<VSisa>")])
;; Fused multiply add.
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 73fd2ce8abb..0bf04feb6c4 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -2184,63 +2184,6 @@
"xvcmpge<sd>p. %x0,%x1,%x2"
[(set_attr "type" "<VStype_simple>")])
-;; Vector select
-(define_insn "vsx_xxsel<mode>"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa"))
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (match_dup 3)
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa"))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
-(define_insn "vsx_xxsel<mode>2"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (not:VSX_L (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa"))
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa")
- (match_dup 3))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x1,%x2,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
-(define_insn "vsx_xxsel<mode>3"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (not:VSX_L (match_dup 3))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa"))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x2,%x1,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
-(define_insn "vsx_xxsel<mode>4"
- [(set (match_operand:VSX_L 0 "vsx_register_operand" "=<VSr>,?wa")
- (ior:VSX_L
- (and:VSX_L
- (match_operand:VSX_L 1 "vsx_register_operand" "<VSr>,wa")
- (match_operand:VSX_L 3 "vsx_register_operand" "<VSr>,wa"))
- (and:VSX_L
- (not:VSX_L (match_dup 3))
- (match_operand:VSX_L 2 "vsx_register_operand" "<VSr>,wa"))))]
- "VECTOR_MEM_VSX_P (<MODE>mode)"
- "xxsel %x0,%x2,%x1,%x3"
- [(set_attr "type" "vecmove")
- (set_attr "isa" "<VSisa>")])
-
;; Copy sign
(define_insn "vsx_copysign<mode>3"
[(set (match_operand:VSX_F 0 "vsx_register_operand" "=wa")
diff --git a/gcc/testsuite/gcc.target/powerpc/builtins-1.c b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
index 2dafa902953..63fbd2e3be1 100644
--- a/gcc/testsuite/gcc.target/powerpc/builtins-1.c
+++ b/gcc/testsuite/gcc.target/powerpc/builtins-1.c
@@ -326,7 +326,7 @@ int main ()
/* { dg-final { scan-assembler-times {\mvpkudus\M} 1 } } */
/* { dg-final { scan-assembler-times "vperm" 4 } } */
/* { dg-final { scan-assembler-times "xvrdpi" 2 } } */
-/* { dg-final { scan-assembler-times "xxsel" 10 } } */
+/* { dg-final { scan-assembler-times "xxsel" 5 } } */
/* { dg-final { scan-assembler-times "xxlxor" 6 } } */
/* { dg-final { scan-assembler-times "divd" 8 { target lp64 } } } */
/* { dg-final { scan-assembler-times "divdu" 2 { target lp64 } } } */
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