[gcc r12-4761] RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern

[gcc r12-4761] RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern

[Kito Cheng]

https://gcc.gnu.org/g:2dc835cd0b5183a0e30b2b052362ad05f5c082b0

commit r12-4761-g2dc835cd0b5183a0e30b2b052362ad05f5c082b0
Author: Kito Cheng <kito.cheng@sifive.com>
Date:   Thu Oct 28 00:27:39 2021 +0800

    RISC-V: Fix wrong predicator for zero_extendsidi2_internal pattern
    
    We're wrongly guard zero_extendsidi2_internal pattern both ZBA and ZBB,
    only ZBA provide zero_extendsidi2 instruction.
    
    gcc/ChangeLog
    
            * config/riscv/riscv.md (zero_extendsidi2_internal): Allow ZBB
            use this pattern.

Diff:
---
 gcc/config/riscv/riscv.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/gcc/config/riscv/riscv.md b/gcc/config/riscv/riscv.md
index dd4c24292f2..225e5b259c1 100644
--- a/gcc/config/riscv/riscv.md
+++ b/gcc/config/riscv/riscv.md
@@ -1311,7 +1311,7 @@
   [(set (match_operand:DI     0 "register_operand"     "=r,r")
 	(zero_extend:DI
 	    (match_operand:SI 1 "nonimmediate_operand" " r,m")))]
-  "TARGET_64BIT && !(TARGET_ZBA || TARGET_ZBB)"
+  "TARGET_64BIT && !TARGET_ZBA"
   "@
    #
    lwu\t%0,%1"