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From: Michael Meissner <meissner@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/meissner/heads/work072)] Revert patches. Date: Wed, 3 Nov 2021 19:21:23 +0000 (GMT) [thread overview] Message-ID: <20211103192123.D9F2A3858C60@sourceware.org> (raw) https://gcc.gnu.org/g:8200636dad8a389ed421410420f5f98e3cdcf42e commit 8200636dad8a389ed421410420f5f98e3cdcf42e Author: Michael Meissner <meissner@linux.ibm.com> Date: Wed Nov 3 15:20:27 2021 -0400 Revert patches. 2021-11-03 Michael Meissner <meissner@the-meissners.org> gcc/ Revert patches. * config/rs6000/predicates.md (vsx_prefixed_constant): Add support for generating XXSPLTIDP. * config/rs6000/rs6000.md (UNSPEC_XXSPLTIDP_CONST): New unspec. (UNSPEC_XXSPLTIW_CONST): New unspec. (movsf_hardfloat): Add support for generating XXSPLTIDP. (mov<mode>_hardfloat32): Likewise. (mov<mode>_hardfloat64): Likewise. (xxspltidp_<mode>_internal): New insns. (xxspltiw_<mode>_internal): New insns. (splitters for SF/DFmode): Add new splitters for XXSPLTIDP. gcc/testsuite/ Revert patches. * gcc.target/powerpc/vec-splat-constant-df.c: New test. * gcc.target/powerpc/vec-splat-constant-sf.c: New test. 2021-11-03 Michael Meissner <meissner@the-meissners.org> gcc/ Revert patches. * config/rs6000/predicates.md (easy_fp_constant): Add support for generating XXSPLTIDP. (vsx_prefixed_constant): Likewise. (easy_vector_constant): Likewise. * config/rs6000/rs6000-protos.h (constant_generates_xxspltidp): New declaration. * config/rs6000/rs6000.c (output_vec_const_move): Add support for generating XXSPLTIDP. (prefixed_xxsplti_p): Likewise. (constant_generates_xxspltidp): New function. * config/rs6000/rs6000.opt (-msplat-float-constant): New debug option. gcc/testsuite/ Revert patches. * gcc.target/powerpc/pr86731-fwrapv-longlong.c: Update insn regex for power10. * gcc.target/powerpc/vec-splat-constant-v2df.c: New test. * gcc.target/powerpc/vec-splat-constant-v2di.c: New test. Diff: --- gcc/config/rs6000/predicates.md | 9 -- gcc/config/rs6000/rs6000-protos.h | 1 - gcc/config/rs6000/rs6000.c | 108 --------------------- gcc/config/rs6000/rs6000.md | 97 ++++-------------- gcc/config/rs6000/rs6000.opt | 4 - .../gcc.target/powerpc/pr86731-fwrapv-longlong.c | 9 +- .../gcc.target/powerpc/vec-splat-constant-df.c | 60 ------------ .../gcc.target/powerpc/vec-splat-constant-sf.c | 60 ------------ .../gcc.target/powerpc/vec-splat-constant-v2df.c | 64 ------------ .../gcc.target/powerpc/vec-splat-constant-v2di.c | 50 ---------- 10 files changed, 22 insertions(+), 440 deletions(-) diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md index d748b11857c..ed6252bd0c4 100644 --- a/gcc/config/rs6000/predicates.md +++ b/gcc/config/rs6000/predicates.md @@ -610,9 +610,6 @@ if (constant_generates_xxspltiw (&vsx_const)) return true; - - if (constant_generates_xxspltidp (&vsx_const)) - return true; } /* Otherwise consider floating point constants hard, so that the @@ -656,9 +653,6 @@ if (constant_generates_xxspltiw (&vsx_const)) return true; - if (constant_generates_xxspltidp (&vsx_const)) - return true; - return false; }) @@ -733,9 +727,6 @@ if (constant_generates_xxspltiw (&vsx_const)) return true; - - if (constant_generates_xxspltidp (&vsx_const)) - return true; } if (TARGET_P9_VECTOR diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index 2d28df7442d..99c6a671289 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -253,7 +253,6 @@ extern bool vec_const_128bit_to_bytes (rtx, machine_mode, vec_const_128bit_type *); extern unsigned constant_generates_lxvkq (vec_const_128bit_type *); extern unsigned constant_generates_xxspltiw (vec_const_128bit_type *); -extern unsigned constant_generates_xxspltidp (vec_const_128bit_type *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 8fde48cf2b3..be24f56eb31 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -7012,13 +7012,6 @@ output_vec_const_move (rtx *operands) operands[2] = GEN_INT (imm); return "xxspltiw %x0,%2"; } - - imm = constant_generates_xxspltidp (&vsx_const); - if (imm) - { - operands[2] = GEN_INT (imm); - return "xxspltidp %x0,%2"; - } } if (TARGET_P9_VECTOR @@ -26816,9 +26809,6 @@ prefixed_xxsplti_p (rtx_insn *insn) { if (constant_generates_xxspltiw (&vsx_const)) return true; - - if (constant_generates_xxspltidp (&vsx_const)) - return true; } return false; @@ -29024,104 +29014,6 @@ constant_generates_xxspltiw (vec_const_128bit_type *vsx_const) return vsx_const->words[0]; } -/* Determine if a vector constant can be loaded with XXSPLTIDP. Return zero if - the XXSPLTIDP instruction cannot be used. Otherwise return the immediate - value to be used with the XXSPLTIDP instruction. */ - -unsigned -constant_generates_xxspltidp (vec_const_128bit_type *vsx_const) -{ - if (!TARGET_SPLAT_FLOAT_CONSTANT || !TARGET_PREFIXED || !TARGET_VSX) - return 0; - - /* Make sure that the two 64-bit segments are the same. */ - if (!vsx_const->all_double_words_same) - return 0; - - /* If the bytes, half words, or words are all the same, don't use XXSPLTIDP. - Use a simpler instruction (XXSPLTIB, VSPLTISB, VSPLTISH, or VSPLTISW). */ - if (vsx_const->all_bytes_same - || vsx_const->all_half_words_same - || vsx_const->all_words_same) - return 0; - - unsigned HOST_WIDE_INT value = vsx_const->double_words[0]; - - /* Avoid values that look like DFmode NaN's, except for the normal NaN bit - pattern and the signalling NaN bit pattern. Recognize infinity and - negative infinity. */ - - /* Bit representation of DFmode normal quiet NaN. */ -#define RS6000_CONST_DF_NAN HOST_WIDE_INT_UC (0x7ff8000000000000) - - /* Bit representation of DFmode normal signaling NaN. */ -#define RS6000_CONST_DF_NANS HOST_WIDE_INT_UC (0x7ff4000000000000) - - /* Bit representation of DFmode positive infinity. */ -#define RS6000_CONST_DF_INF HOST_WIDE_INT_UC (0x7ff0000000000000) - - /* Bit representation of DFmode negative infinity. */ -#define RS6000_CONST_DF_NEG_INF HOST_WIDE_INT_UC (0xfff0000000000000) - - if (value != RS6000_CONST_DF_NAN - && value != RS6000_CONST_DF_NANS - && value != RS6000_CONST_DF_INF - && value != RS6000_CONST_DF_NEG_INF) - { - /* The IEEE 754 64-bit floating format has 1 bit for sign, 11 bits for - the exponent, and 52 bits for the mantissa (not counting the hidden - bit used for normal numbers). NaN values have the exponent set to all - 1 bits, and the mantissa non-zero (mantissa == 0 is infinity). */ - - int df_exponent = (value >> 52) & 0x7ff; - unsigned HOST_WIDE_INT df_mantissa - = value & ((HOST_WIDE_INT_1U << 52) - HOST_WIDE_INT_1U); - - if (df_exponent == 0x7ff && df_mantissa != 0) /* other NaNs. */ - return 0; - - /* Avoid values that are DFmode subnormal values. Subnormal numbers have - the exponent all 0 bits, and the mantissa non-zero. If the value is - subnormal, then the hidden bit in the mantissa is not set. */ - if (df_exponent == 0 && df_mantissa != 0) /* subnormal. */ - return 0; - } - - /* Change the representation to DFmode constant. */ - long df_words[2] = { vsx_const->words[0], vsx_const->words[1] }; - - /* real_from_target takes the target words in target order. */ - if (!BYTES_BIG_ENDIAN) - std::swap (df_words[0], df_words[1]); - - REAL_VALUE_TYPE rv_type; - real_from_target (&rv_type, df_words, DFmode); - - const REAL_VALUE_TYPE *rv = &rv_type; - - /* Validate that the number can be stored as a SFmode value. */ - if (!exact_real_truncate (SFmode, rv)) - return 0; - - /* Validate that the number is not a SFmode subnormal value (exponent is 0, - mantissa field is non-zero) which is undefined for the XXSPLTIDP - instruction. */ - long sf_value; - real_to_target (&sf_value, rv, SFmode); - - /* IEEE 754 32-bit values have 1 bit for the sign, 8 bits for the exponent, - and 23 bits for the mantissa. Subnormal numbers have the exponent all - 0 bits, and the mantissa non-zero. */ - long sf_exponent = (sf_value >> 23) & 0xFF; - long sf_mantissa = sf_value & 0x7FFFFF; - - if (sf_exponent == 0 && sf_mantissa != 0) - return 0; - - /* Return the immediate to be used. */ - return sf_value; -} - \f struct gcc_target targetm = TARGET_INITIALIZER; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 4122acb98cf..3a7bcd2426e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -156,8 +156,6 @@ UNSPEC_PEXTD UNSPEC_HASHST UNSPEC_HASHCHK - UNSPEC_XXSPLTIDP_CONST - UNSPEC_XXSPLTIW_CONST ]) ;; @@ -7766,17 +7764,17 @@ ;; ;; LWZ LFS LXSSP LXSSPX STFS STXSSP ;; STXSSPX STW XXLXOR LI FMR XSCPSGNDP -;; MR MT<x> MF<x> NOP XXSPLTIDP +;; MR MT<x> MF<x> NOP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa, m, wY, Z, m, wa, !r, f, wa, - !r, *c*l, !r, *h, wa") + !r, *c*l, !r, *h") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa, r, j, j, f, wa, - r, r, *h, 0, eP"))] + r, r, *h, 0"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -7798,16 +7796,15 @@ mr %0,%1 mt%0 %1 mf%1 %0 - nop - #" + nop" [(set_attr "type" "load, fpload, fpload, fpload, fpstore, fpstore, fpstore, store, veclogical, integer, fpsimple, fpsimple, - *, mtjmpr, mfjmpr, *, vecperm") + *, mtjmpr, mfjmpr, *") (set_attr "isa" "*, *, p9v, p8v, *, p9v, p8v, *, *, *, *, *, - *, *, *, *, p10")]) + *, *, *, *")]) ;; LWZ LFIWZX STW STFIWX MTVSRWZ MFVSRWZ ;; FMR MR MT%0 MF%1 NOP @@ -8067,18 +8064,18 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSD STXSD XXLOR XXLXOR GPR<-0 -;; LWZ STW MR XXSPLTIDP +;; LWZ STW MR (define_insn "*mov<mode>_hardfloat32" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, <f64_p9>, wY, <f64_av>, Z, <f64_vsx>, <f64_vsx>, !r, - Y, r, !r, wa") + Y, r, !r") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, <f64_p9>, Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>, - r, Y, r, eP"))] + r, Y, r"))] "! TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -8095,21 +8092,20 @@ # # # - # #" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, two, - store, load, two, vecperm") + store, load, two") (set_attr "size" "64") (set_attr "length" "*, *, *, *, *, *, *, *, *, 8, - 8, 8, 8, *") + 8, 8, 8") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, - *, *, *, p10")]) + *, *, *")]) ;; STW LWZ MR G-const H-const F-const @@ -8136,19 +8132,19 @@ ;; STFD LFD FMR LXSD STXSD ;; LXSDX STXSDX XXLOR XXLXOR LI 0 ;; STD LD MR MT{CTR,LR} MF{CTR,LR} -;; NOP MFVSRD MTVSRD XXSPLTIDP +;; NOP MFVSRD MTVSRD (define_insn "*mov<mode>_hardfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, <f64_p9>, wY, <f64_av>, Z, <f64_vsx>, <f64_vsx>, !r, YZ, r, !r, *c*l, !r, - *h, r, <f64_dm>, wa") + *h, r, <f64_dm>") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, <f64_p9>, Z, <f64_av>, <f64_vsx>, <zero_fp>, <zero_fp>, r, YZ, r, r, *h, - 0, <f64_dm>, r, eP"))] + 0, <f64_dm>, r"))] "TARGET_POWERPC64 && TARGET_HARD_FLOAT && (gpc_reg_operand (operands[0], <MODE>mode) || gpc_reg_operand (operands[1], <MODE>mode))" @@ -8170,19 +8166,18 @@ mf%1 %0 nop mfvsrd %0,%x1 - mtvsrd %x0,%1 - #" + mtvsrd %x0,%1" [(set_attr "type" "fpstore, fpload, fpsimple, fpload, fpstore, fpload, fpstore, veclogical, veclogical, integer, store, load, *, mtjmpr, mfjmpr, - *, mfvsr, mtvsr, vecperm") + *, mfvsr, mtvsr") (set_attr "size" "64") (set_attr "isa" "*, *, *, p9v, p9v, p7v, p7v, *, *, *, *, *, *, *, *, - *, p8v, p8v, p10")]) + *, p8v, p8v")]) ;; STD LD MR MT<SPR> MF<SPR> G-const ;; H-const F-const Special @@ -8216,62 +8211,6 @@ (set_attr "length" "*, *, *, *, *, 8, 12, 16, *")]) - -;; Split the VSX prefixed instruction to support SFmode and DFmode scalar -;; constants that look like DFmode floating point values where both elements -;; are the same. The constant has to be expressible as a SFmode constant that -;; is not a SFmode denormal value. -;; -;; We don't need splitters for the 128-bit types, since the function -;; rs6000_output_move_128bit handles the generation of XXSPLTIDP. -(define_insn "xxspltidp_<mode>_internal" - [(set (match_operand:SFDF 0 "register_operand" "=wa") - (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] - UNSPEC_XXSPLTIDP_CONST))] - "TARGET_POWER10" - "xxspltidp %x0,%1" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - -(define_insn "xxspltiw_<mode>_internal" - [(set (match_operand:SFDF 0 "register_operand" "=wa") - (unspec:SFDF [(match_operand:SI 1 "c32bit_cint_operand" "n")] - UNSPEC_XXSPLTIW_CONST))] - "TARGET_POWER10" - "xxspltiw %x0,%1" - [(set_attr "type" "vecperm") - (set_attr "prefixed" "yes")]) - -(define_split - [(set (match_operand:SFDF 0 "vsx_register_operand") - (match_operand:SFDF 1 "vsx_prefixed_constant"))] - "TARGET_POWER10" - [(pc)] -{ - rtx dest = operands[0]; - rtx src = operands[1]; - vec_const_128bit_type vsx_const; - - if (!vec_const_128bit_to_bytes (src, <MODE>mode, &vsx_const)) - gcc_unreachable (); - - unsigned imm = constant_generates_xxspltidp (&vsx_const); - if (imm) - { - emit_insn (gen_xxspltidp_<mode>_internal (dest, GEN_INT (imm))); - DONE; - } - - imm = constant_generates_xxspltiw (&vsx_const); - if (imm) - { - emit_insn (gen_xxspltiw_<mode>_internal (dest, GEN_INT (imm))); - DONE; - } - - else - gcc_unreachable (); -}) \f (define_expand "mov<mode>" [(set (match_operand:FMOVE128 0 "general_operand") diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index c1d661d7e6b..ec7b106fddb 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -644,10 +644,6 @@ msplat-word-constant Target Var(TARGET_SPLAT_WORD_CONSTANT) Init(1) Save Generate (do not generate) code that uses the XXSPLTIW instruction. -msplat-float-constant -Target Var(TARGET_SPLAT_FLOAT_CONSTANT) Init(1) Save -Generate (do not generate) code that uses the XXSPLTIDP instruction. - mieee128-constant Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save Generate (do not generate) code that uses the LXVKQ instruction. diff --git a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c index dcb30e1d886..bd1502bb30a 100644 --- a/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c +++ b/gcc/testsuite/gcc.target/powerpc/pr86731-fwrapv-longlong.c @@ -24,12 +24,11 @@ vector signed long long splats4(void) return (vector signed long long) vec_sl(mzero, mzero); } -/* Codegen will consist of splat and shift instructions for most types. If - folding is enabled, the vec_sl tests using vector long long type will - generate a lvx instead of a vspltisw+vsld pair. On power10, it will - generate a xxspltidp instruction instead of the lvx. */ +/* Codegen will consist of splat and shift instructions for most types. + If folding is enabled, the vec_sl tests using vector long long type will + generate a lvx instead of a vspltisw+vsld pair. */ /* { dg-final { scan-assembler-times {\mvspltis[bhw]\M} 0 } } */ /* { dg-final { scan-assembler-times {\mvsl[bhwd]\M} 0 } } */ -/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M|\mxxspltidp\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mp?lxv\M|\mlxv\M|\mlxvd2x\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c deleted file mode 100644 index 8f6e176f9af..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-df.c +++ /dev/null @@ -1,60 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <math.h> - -/* Test generating DFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -double -scalar_double_0 (void) -{ - return 0.0; /* XXSPLTIB or XXLXOR. */ -} - -double -scalar_double_1 (void) -{ - return 1.0; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -double -scalar_double_m0 (void) -{ - return -0.0; /* XXSPLTIDP. */ -} - -double -scalar_double_nan (void) -{ - return __builtin_nan (""); /* XXSPLTIDP. */ -} - -double -scalar_double_inf (void) -{ - return __builtin_inf (); /* XXSPLTIDP. */ -} - -double -scalar_double_m_inf (void) /* XXSPLTIDP. */ -{ - return - __builtin_inf (); -} -#endif - -double -scalar_double_pi (void) -{ - return M_PI; /* PLFD. */ -} - -double -scalar_double_denorm (void) -{ - return 0x1p-149f; /* PLFD. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c deleted file mode 100644 index 72504bdfbbd..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-sf.c +++ /dev/null @@ -1,60 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <math.h> - -/* Test generating SFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -float -scalar_float_0 (void) -{ - return 0.0f; /* XXSPLTIB or XXLXOR. */ -} - -float -scalar_float_1 (void) -{ - return 1.0f; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -float -scalar_float_m0 (void) -{ - return -0.0f; /* XXSPLTIDP. */ -} - -float -scalar_float_nan (void) -{ - return __builtin_nanf (""); /* XXSPLTIDP. */ -} - -float -scalar_float_inf (void) -{ - return __builtin_inff (); /* XXSPLTIDP. */ -} - -float -scalar_float_m_inf (void) /* XXSPLTIDP. */ -{ - return - __builtin_inff (); -} -#endif - -float -scalar_float_pi (void) -{ - return (float)M_PI; /* XXSPLTIDP. */ -} - -float -scalar_float_denorm (void) -{ - return 0x1p-149f; /* PLFS. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 6 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c deleted file mode 100644 index 82ffc86f8aa..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2df.c +++ /dev/null @@ -1,64 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -#include <math.h> - -/* Test generating V2DFmode constants with the ISA 3.1 (power10) XXSPLTIDP - instruction. */ - -vector double -v2df_double_0 (void) -{ - return (vector double) { 0.0, 0.0 }; /* XXSPLTIB or XXLXOR. */ -} - -vector double -v2df_double_1 (void) -{ - return (vector double) { 1.0, 1.0 }; /* XXSPLTIDP. */ -} - -#ifndef __FAST_MATH__ -vector double -v2df_double_m0 (void) -{ - return (vector double) { -0.0, -0.0 }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_nan (void) -{ - return (vector double) { __builtin_nan (""), - __builtin_nan ("") }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_inf (void) -{ - return (vector double) { __builtin_inf (), - __builtin_inf () }; /* XXSPLTIDP. */ -} - -vector double -v2df_double_m_inf (void) -{ - return (vector double) { - __builtin_inf (), - - __builtin_inf () }; /* XXSPLTIDP. */ -} -#endif - -vector double -v2df_double_pi (void) -{ - return (vector double) { M_PI, M_PI }; /* PLVX. */ -} - -vector double -v2df_double_denorm (void) -{ - return (vector double) { (double)0x1p-149f, - (double)0x1p-149f }; /* PLVX. */ -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 5 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c b/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c deleted file mode 100644 index 4d44f943d26..00000000000 --- a/gcc/testsuite/gcc.target/powerpc/vec-splat-constant-v2di.c +++ /dev/null @@ -1,50 +0,0 @@ -/* { dg-do compile } */ -/* { dg-require-effective-target power10_ok } */ -/* { dg-options "-mdejagnu-cpu=power10 -O2" } */ - -/* Test generating V2DImode constants that have the same bit pattern as - V2DFmode constants that can be loaded with the XXSPLTIDP instruction with - the ISA 3.1 (power10). */ - -vector long long -vector_0 (void) -{ - /* XXSPLTIB or XXLXOR. */ - return (vector long long) { 0LL, 0LL }; -} - -vector long long -vector_1 (void) -{ - /* XXSPLTIB and VEXTSB2D. */ - return (vector long long) { 1LL, 1LL }; -} - -/* 0x8000000000000000LL is the bit pattern for -0.0, which can be generated - with XXSPLTISDP. */ -vector long long -vector_float_neg_0 (void) -{ - /* XXSPLTIDP. */ - return (vector long long) { 0x8000000000000000LL, 0x8000000000000000LL }; -} - -/* 0x3ff0000000000000LL is the bit pattern for 1.0 which can be generated with - XXSPLTISDP. */ -vector long long -vector_float_1_0 (void) -{ - /* XXSPLTIDP. */ - return (vector long long) { 0x3ff0000000000000LL, 0x3ff0000000000000LL }; -} - -/* 0x400921fb54442d18LL is the bit pattern for PI, which cannot be generated - with XXSPLTIDP. */ -vector long long -scalar_pi (void) -{ - /* PLXV. */ - return (vector long long) { 0x400921fb54442d18LL, 0x400921fb54442d18LL }; -} - -/* { dg-final { scan-assembler-times {\mxxspltidp\M} 2 } } */
next reply other threads:[~2021-11-03 19:21 UTC|newest] Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top 2021-11-03 19:21 Michael Meissner [this message] 2021-11-11 2:47 Michael Meissner
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