[gcc(refs/users/meissner/heads/work072)] Add support for power10 zero cycle moves for switches.

[Michael Meissner <meissner@gcc.gnu.org>]

https://gcc.gnu.org/g:700ef1cec94719ff3dcb9407d5ac371be96f5905

commit 700ef1cec94719ff3dcb9407d5ac371be96f5905
Author: Michael Meissner <meissner@linux.ibm.com>
Date:   Wed Nov 10 19:17:45 2021 -0500

    Add support for power10 zero cycle moves for switches.
    
    Power10 will fuse adjacenet 'mtctr' and 'bctr' instructions to form zero
    cycle moves.  This code exploits this fusion opportunity.
    
    2021-11-10  Michael Meissner  <meissner@the-meissners.org>
    
            * config/rs6000/rs6000.c (rs6000_option_override_internal): Add
            support for -mpower10-fusion-zero-cycle.
            * config/rs6000/rs6000.md (tablejump<mode>_normal): Likewise.
            (tablejump<mode>_absolute): Likewise.
            (tablejump<mode>_insn_zero_cycle): New insn.
            * config/rs6000/rs6000.opt (-mpower10-fusion-zero-cycle): New
            debug switch.

Diff:
---
 gcc/config/rs6000/rs6000.c   |  4 ++++
 gcc/config/rs6000/rs6000.md  | 24 ++++++++++++++++++++++--
 gcc/config/rs6000/rs6000.opt |  4 ++++
 3 files changed, 30 insertions(+), 2 deletions(-)

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index 8fde48cf2b3..92736d4cca4 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -4503,6 +4503,10 @@ rs6000_option_override_internal (bool global_init_p)
       && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_2STORE) == 0)
     rs6000_isa_flags |= OPTION_MASK_P10_FUSION_2STORE;
 
+  if (TARGET_POWER10
+      && (rs6000_isa_flags_explicit & OPTION_MASK_P10_FUSION_ZERO_CYCLE) == 0)
+    rs6000_isa_flags |= OPTION_MASK_P10_FUSION_ZERO_CYCLE;
+
   /* Turn off vector pair/mma options on non-power10 systems.  */
   else if (!TARGET_POWER10 && TARGET_MMA)
     {
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 4122acb98cf..fe835e1a79f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -13116,7 +13116,11 @@
   rtx addr = gen_reg_rtx (Pmode);
 
   emit_insn (gen_add<mode>3 (addr, off, lab));
-  emit_jump_insn (gen_tablejump_insn_normal (Pmode, addr, operands[1]));
+  rtx insn = (TARGET_P10_FUSION && TARGET_P10_FUSION_ZERO_CYCLE
+	      ? gen_tablejump_insn_zero_cycle (Pmode, addr, operands[1])
+	      : gen_tablejump_insn_normal (Pmode, addr, operands[1]));
+
+  emit_jump_insn (insn);
   DONE;
 })
 
@@ -13128,7 +13132,11 @@
   rtx addr = gen_reg_rtx (Pmode);
   emit_move_insn (addr, operands[0]);
 
-  emit_jump_insn (gen_tablejump_insn_normal (Pmode, addr, operands[1]));
+  rtx insn = (TARGET_P10_FUSION && TARGET_P10_FUSION_ZERO_CYCLE
+	      ? gen_tablejump_insn_zero_cycle (Pmode, addr, operands[1])
+	      : gen_tablejump_insn_normal (Pmode, addr, operands[1]));
+
+  emit_jump_insn (insn);
   DONE;
 })
 
@@ -13177,6 +13185,18 @@
   "b%T0"
   [(set_attr "type" "jmpreg")])
 
+;; Version of indirect jump that fuses the mtctr to bctr to achieve 0 cycle
+;; moves on Power10.
+(define_insn "@tablejump<mode>_insn_zero_cycle"
+  [(set (pc)
+	(match_operand:P 0 "register_operand" "r,r"))
+   (use (label_ref (match_operand 1)))
+   (clobber (match_scratch:P 2 "=c,*l"))]
+  "rs6000_speculate_indirect_jumps"
+  "mt%T2 %0\;b%T2"
+  [(set_attr "type" "jmpreg")
+   (set_attr "length" "8")])
+
 (define_insn "@tablejump<mode>_insn_nospec"
   [(set (pc)
 	(match_operand:P 0 "register_operand" "c,*l"))
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index c1d661d7e6b..c0d5e1d45a6 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -518,6 +518,10 @@ mpower10-fusion-2store
 Target Undocumented Mask(P10_FUSION_2STORE) Var(rs6000_isa_flags)
 Fuse certain store operations together for better performance on power10.
 
+mpower10-fusion-zero-cycle
+Target Undocumented Mask(P10_FUSION_ZERO_CYCLE) Var(rs6000_isa_flags)
+Fuse move to special register and jump for better performance on power10.
+
 mcrypto
 Target Mask(CRYPTO) Var(rs6000_isa_flags)
 Use ISA 2.07 Category:Vector.AES and Category:Vector.SHA2 instructions.