From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1652) id 60965385C401; Tue, 16 Nov 2021 14:07:49 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 60965385C401 Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit From: Christophe Lyon To: gcc-cvs@gcc.gnu.org Subject: [gcc(refs/users/clyon/heads/mve-autovec)] WIP: add new constraint to thumb2_movhi* patterns, add assorted fixes X-Act-Checkin: gcc X-Git-Author: Christophe Lyon X-Git-Refname: refs/users/clyon/heads/mve-autovec X-Git-Oldrev: 33809fd5dbf87565bc899c1435a3e8a1079704b5 X-Git-Newrev: 7597f7f288a8eeff0502695e7f76e806f9758c6d Message-Id: <20211116140749.60965385C401@sourceware.org> Date: Tue, 16 Nov 2021 14:07:49 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 16 Nov 2021 14:07:49 -0000 https://gcc.gnu.org/g:7597f7f288a8eeff0502695e7f76e806f9758c6d commit 7597f7f288a8eeff0502695e7f76e806f9758c6d Author: Christophe Lyon Date: Tue Nov 16 13:58:33 2021 +0000 WIP: add new constraint to thumb2_movhi* patterns, add assorted fixes Diff: --- gcc/config/arm/arm.c | 29 ++++++++++++++++++++++++++++- gcc/config/arm/constraints.md | 6 ++++++ gcc/config/arm/vfp.md | 12 ++++++++---- 3 files changed, 42 insertions(+), 5 deletions(-) diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 37b6f230ba4..79ec639e088 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -12744,7 +12744,8 @@ simd_valid_immediate (rtx op, machine_mode mode, int inverse, innersize = GET_MODE_UNIT_SIZE (mode); /* Only support 128-bit vectors for MVE. */ - if (TARGET_HAVE_MVE && (!vector || n_elts * innersize != 16)) + if (TARGET_HAVE_MVE + && (!vector || (innersize == 1) || n_elts * innersize != 16)) return -1; /* Vectors of float constants. */ @@ -13109,6 +13110,30 @@ neon_vdup_constant (rtx vals, bool generate) return gen_vec_duplicate (mode, x); } +/* FIXME */ +rtx mve_const_bool_vec_to_hi (rtx const_vec) +{ + int n_elts = GET_MODE_NUNITS ( GET_MODE (const_vec)); + int repeat = 16 / n_elts; + int i; + int hi_val = 0; + + for (i = 0; i < n_elts; i++) + { + rtx el = CONST_VECTOR_ELT (const_vec, i); + unsigned HOST_WIDE_INT elpart; + + gcc_assert (CONST_INT_P (el)); + elpart = INTVAL (el); + + for (int j = 0; j < repeat; j++) + { + hi_val |= elpart << (i * repeat + j); + } + } + return GEN_INT (hi_val); +} + /* Return a non-NULL RTX iff VALS, which is a PARALLEL containing only constants (for vec_init) or CONST_VECTOR, can be effeciently loaded into a register. @@ -13149,6 +13174,8 @@ neon_make_constant (rtx vals, bool generate) && simd_immediate_valid_for_move (const_vec, mode, NULL, NULL)) /* Load using VMOV. On Cortex-A8 this takes one cycle. */ return const_vec; + else if (TARGET_HAVE_MVE && (GET_MODE_UNIT_SIZE (mode) == 1)) + return mve_const_bool_vec_to_hi (const_vec); else if ((target = neon_vdup_constant (vals, generate)) != NULL_RTX) /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON pipeline cycle; creating the constant takes one or two ARM diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index a5a19a7ed5b..acc447ba0f0 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -312,6 +312,12 @@ (and (match_code "const_vector") (match_test "(TARGET_NEON || TARGET_HAVE_MVE) && op == CONST0_RTX (mode)"))) +(define_constraint "DB" + "@internal + In ARM/Thumb-2 state with MVE a constant vector of booleans." + (and (match_code "const_vector") + (match_test "TARGET_HAVE_MVE && GET_MODE_CLASS (mode) == MODE_VECTOR_BOOL"))) + (define_constraint "Da" "@internal In ARM/Thumb-2 state a const_int, const_double or const_vector that can diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index 9c357cc0389..efbd919ed2c 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -76,7 +76,7 @@ (match_operand:MVE_7_HI 0 "nonimmediate_operand" "=rk, r, l, r, m, r, *t, r, *t, Up, r") (match_operand:MVE_7_HI 1 "general_operand" - "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] + "rk, IDB, Py, n, r, m, r, *t, *t, r, Up"))] "TARGET_THUMB2 && TARGET_VFP_BASE && !TARGET_VFP_FP16INST && (register_operand (operands[0], mode) @@ -85,9 +85,11 @@ switch (which_alternative) { case 0: - case 1: case 2: return "mov%?\t%0, %1\t%@ movhi"; + case 1: + operands[1] = gen_lowpart (HImode, operands[1]); + return "mov%?\t%0, %1\t%@ movhi"; case 3: return "movw%?\t%0, %L1\t%@ movhi"; case 4: @@ -176,7 +178,7 @@ (match_operand:MVE_7_HI 0 "nonimmediate_operand" "=rk, r, l, r, m, r, *t, r, *t, Up, r") (match_operand:MVE_7_HI 1 "general_operand" - "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] + "rk, IDB, Py, n, r, m, r, *t, *t, r, Up"))] "TARGET_THUMB2 && (TARGET_VFP_FP16INST || TARGET_HAVE_MVE) && (register_operand (operands[0], mode) || register_operand (operands[1], mode))" @@ -184,9 +186,11 @@ switch (which_alternative) { case 0: - case 1: case 2: return "mov%?\t%0, %1\t%@ movhi"; + case 1: + operands[1] = gen_lowpart (HImode, operands[1]); + return "mov%?\t%0, %1\t%@ movhi"; case 3: return "movw%?\t%0, %L1\t%@ movhi"; case 4: