From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7820) id DC77E385841C; Wed, 17 Nov 2021 14:00:14 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org DC77E385841C MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Przemyslaw Wirkus To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-5339] aarch64: Add new vector mode V8DI X-Act-Checkin: gcc X-Git-Author: Przemyslaw Wirkus X-Git-Refname: refs/heads/master X-Git-Oldrev: 4e6bf0b9dd5585df1a1472d6a93b9fff72fe2524 X-Git-Newrev: dd159a4167ca19b5ff26e7156333c88e854943bf Message-Id: <20211117140014.DC77E385841C@sourceware.org> Date: Wed, 17 Nov 2021 14:00:14 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 17 Nov 2021 14:00:15 -0000 https://gcc.gnu.org/g:dd159a4167ca19b5ff26e7156333c88e854943bf commit r12-5339-gdd159a4167ca19b5ff26e7156333c88e854943bf Author: Przemyslaw Wirkus Date: Wed Nov 17 13:38:24 2021 +0000 aarch64: Add new vector mode V8DI This patch is adding new V8DI mode which will be used with new Armv8.7-A LS64 extension intrinsics. gcc/ChangeLog: * config/aarch64/aarch64-modes.def (VECTOR_MODE): New V8DI mode. * config/aarch64/aarch64.c (aarch64_hard_regno_mode_ok): Handle V8DImode. * config/aarch64/iterators.md (define_mode_attr nunits): Add entry for V8DI. Diff: --- gcc/config/aarch64/aarch64-modes.def | 5 +++++ gcc/config/aarch64/aarch64.c | 4 ++++ gcc/config/aarch64/iterators.md | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/gcc/config/aarch64/aarch64-modes.def b/gcc/config/aarch64/aarch64-modes.def index ac97d222789..f0265bd15b2 100644 --- a/gcc/config/aarch64/aarch64-modes.def +++ b/gcc/config/aarch64/aarch64-modes.def @@ -81,6 +81,11 @@ INT_MODE (OI, 32); INT_MODE (CI, 48); INT_MODE (XI, 64); +/* V8DI mode. */ +VECTOR_MODE_WITH_PREFIX (V, INT, DI, 8, 5); + +ADJUST_ALIGNMENT (V8DI, 8); + /* Define Advanced SIMD modes for structures of 2, 3 and 4 d-registers. */ #define ADV_SIMD_D_REG_STRUCT_MODES(NVECS, VB, VH, VS, VD) \ VECTOR_MODES_WITH_PREFIX (V##NVECS##x, INT, 8, 3); \ diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index d8410fc52f2..7389b5953dc 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -3394,6 +3394,10 @@ aarch64_hard_regno_nregs (unsigned regno, machine_mode mode) static bool aarch64_hard_regno_mode_ok (unsigned regno, machine_mode mode) { + if (mode == V8DImode) + return IN_RANGE (regno, R0_REGNUM, R23_REGNUM) + && multiple_p (regno - R0_REGNUM, 2); + if (GET_MODE_CLASS (mode) == MODE_CC) return regno == CC_REGNUM; diff --git a/gcc/config/aarch64/iterators.md b/gcc/config/aarch64/iterators.md index a9842b3bddf..2c58d5570ae 100644 --- a/gcc/config/aarch64/iterators.md +++ b/gcc/config/aarch64/iterators.md @@ -1062,7 +1062,7 @@ (define_mode_attr nunits [(V8QI "8") (V16QI "16") (V4HI "4") (V8HI "8") (V2SI "2") (V4SI "4") - (V2DI "2") + (V2DI "2") (V8DI "8") (V4HF "4") (V8HF "8") (V4BF "4") (V8BF "8") (V2SF "2") (V4SF "4")