From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 7808) id 46DBA3858405; Tue, 23 Nov 2021 08:33:52 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 46DBA3858405 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: HaoChen Gui To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-5463] rs6000: Optimize code generation of vec_reve [PR100868] X-Act-Checkin: gcc X-Git-Author: Haochen Gui X-Git-Refname: refs/heads/master X-Git-Oldrev: 1ddf11d3647f68e0c31016935f19d843d54030b4 X-Git-Newrev: f4eae6450e46224454ce067ac43bd7e9f66fc18b Message-Id: <20211123083352.46DBA3858405@sourceware.org> Date: Tue, 23 Nov 2021 08:33:52 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 23 Nov 2021 08:33:52 -0000 https://gcc.gnu.org/g:f4eae6450e46224454ce067ac43bd7e9f66fc18b commit r12-5463-gf4eae6450e46224454ce067ac43bd7e9f66fc18b Author: Haochen Gui Date: Wed Nov 17 16:16:02 2021 +0800 rs6000: Optimize code generation of vec_reve [PR100868] gcc/ PR target/100868 * config/rs6000/altivec.md (altivec_vreve2 for VEC_K): Use xxbrq for v16qi, xxbrq + xxbrh for v8hi and xxbrq + xxbrw for v4si or v4sf when p9_vector is set. (altivec_vreve2 for VEC_64): Defined. Implemented by xxswapd. gcc/testsuite/ PR target/100868 * gcc.target/powerpc/vec_reve_1.c: New test. * gcc.target/powerpc/vec_reve_2.c: Likewise. Diff: --- gcc/config/rs6000/altivec.md | 46 +++++++++++++++++++++++++-- gcc/testsuite/gcc.target/powerpc/vec_reve_1.c | 17 ++++++++++ gcc/testsuite/gcc.target/powerpc/vec_reve_2.c | 29 +++++++++++++++++ 3 files changed, 90 insertions(+), 2 deletions(-) diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md index a057218aa28..ef432112333 100644 --- a/gcc/config/rs6000/altivec.md +++ b/gcc/config/rs6000/altivec.md @@ -3984,12 +3984,43 @@ DONE; }) +;; Vector reverse elements for V16QI V8HI V4SI V4SF (define_expand "altivec_vreve2" - [(set (match_operand:VEC_A 0 "register_operand" "=v") - (unspec:VEC_A [(match_operand:VEC_A 1 "register_operand" "v")] + [(set (match_operand:VEC_K 0 "register_operand" "=v") + (unspec:VEC_K [(match_operand:VEC_K 1 "register_operand" "v")] UNSPEC_VREVEV))] "TARGET_ALTIVEC" { + if (TARGET_P9_VECTOR) + { + if (mode == V16QImode) + emit_insn (gen_p9_xxbrq_v16qi (operands[0], operands[1])); + else if (mode == V8HImode) + { + rtx subreg1 = simplify_gen_subreg (V1TImode, operands[1], + mode, 0); + rtx temp = gen_reg_rtx (V1TImode); + emit_insn (gen_p9_xxbrq_v1ti (temp, subreg1)); + rtx subreg2 = simplify_gen_subreg (mode, temp, + V1TImode, 0); + emit_insn (gen_p9_xxbrh_v8hi (operands[0], subreg2)); + } + else /* V4SI and V4SF. */ + { + rtx subreg1 = simplify_gen_subreg (V1TImode, operands[1], + mode, 0); + rtx temp = gen_reg_rtx (V1TImode); + emit_insn (gen_p9_xxbrq_v1ti (temp, subreg1)); + rtx subreg2 = simplify_gen_subreg (mode, temp, + V1TImode, 0); + if (mode == V4SImode) + emit_insn (gen_p9_xxbrw_v4si (operands[0], subreg2)); + else + emit_insn (gen_p9_xxbrw_v4sf (operands[0], subreg2)); + } + DONE; + } + int i, j, size, num_elements; rtvec v = rtvec_alloc (16); rtx mask = gen_reg_rtx (V16QImode); @@ -4008,6 +4039,17 @@ DONE; }) +;; Vector reverse elements for V2DI V2DF +(define_expand "altivec_vreve2" + [(set (match_operand:VEC_64 0 "register_operand" "=v") + (unspec:VEC_64 [(match_operand:VEC_64 1 "register_operand" "v")] + UNSPEC_VREVEV))] + "TARGET_ALTIVEC" +{ + emit_insn (gen_xxswapd_ (operands[0], operands[1])); + DONE; +}) + ;; Vector SIMD PEM v2.06c defines LVLX, LVLXL, LVRX, LVRXL, ;; STVLX, STVLXL, STVVRX, STVRXL are available only on Cell. (define_insn "altivec_lvlx" diff --git a/gcc/testsuite/gcc.target/powerpc/vec_reve_1.c b/gcc/testsuite/gcc.target/powerpc/vec_reve_1.c new file mode 100644 index 00000000000..120c318ddfa --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_reve_1.c @@ -0,0 +1,17 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_altivec_ok } */ +/* { dg-options "-O2 -maltivec" } */ + +#include + +vector double foo1 (vector double a) +{ + return vec_reve (a); +} + +vector long long foo2 (vector long long a) +{ + return vec_reve (a); +} + +/* { dg-final { scan-assembler-times {\mxxpermdi\M} 2 } } */ diff --git a/gcc/testsuite/gcc.target/powerpc/vec_reve_2.c b/gcc/testsuite/gcc.target/powerpc/vec_reve_2.c new file mode 100644 index 00000000000..966193951c3 --- /dev/null +++ b/gcc/testsuite/gcc.target/powerpc/vec_reve_2.c @@ -0,0 +1,29 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target powerpc_p9vector_ok } */ +/* { dg-options "-mdejagnu-cpu=power9 -O2" } */ + +#include + +vector int foo1 (vector int a) +{ + return vec_reve (a); +} + +vector float foo2 (vector float a) +{ + return vec_reve (a); +} + +vector short foo3 (vector short a) +{ + return vec_reve (a); +} + +vector char foo4 (vector char a) +{ + return vec_reve (a); +} + +/* { dg-final { scan-assembler-times {\mxxbrq\M} 4 } } */ +/* { dg-final { scan-assembler-times {\mxxbrw\M} 2 } } */ +/* { dg-final { scan-assembler-times {\mxxbrh\M} 1 } } */