[gcc(refs/vendors/ARM/heads/morello)] morello: Set LSB on label in casesi pattern

[Matthew Malcomson <matmal01@gcc.gnu.org>]

https://gcc.gnu.org/g:fce30daf2773f194347363b27f47e02d01c0c7ba

commit fce30daf2773f194347363b27f47e02d01c0c7ba
Author: Stam Markianos-Wright <stam.markianos-wright@arm.com>
Date:   Wed Oct 20 09:55:33 2021 +0100

    morello: Set LSB on label in casesi pattern
    
    The `casesi` backend pattern outputs through the aarch64_output_casesi
    function that emits some manual assembly, which includes an `adr`
    instruction.
    
    The address of the label whose address is taken does not have the LSB
    set, so if that address is branched to, the processor exits C64 state,
    which causes an exception to be raised shortly after.
    
    This patch adds a `+1` after the label in the `addr` instruction, which
    sets the LSB on the address, thus preserving the C64 state.

Diff:
---
 gcc/config/aarch64/aarch64.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index c60939ebe4f..22bd98ddd2e 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -11776,7 +11776,8 @@ aarch64_output_casesi (rtx *operands)
   output_asm_insn (patterns[index][0], operands);
   ASM_GENERATE_INTERNAL_LABEL (label, "Lrtx", CODE_LABEL_NUMBER (operands[2]));
   snprintf (buf, sizeof (buf),
-	    "adr\t%%4, %s", targetm.strip_name_encoding (label));
+	    "adr\t%%4, %s%s", targetm.strip_name_encoding (label),
+	     TARGET_CAPABILITY_PURE ? "+1" : "");
   output_asm_insn (buf, operands);
   output_asm_insn (patterns[index][1], operands);
   output_asm_insn ("br\t%3", operands);