From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 1363) id 714BF3858C27; Fri, 24 Dec 2021 16:10:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 714BF3858C27 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain; charset="utf-8" From: Uros Bizjak To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-6113] i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] X-Act-Checkin: gcc X-Git-Author: Uros Bizjak X-Git-Refname: refs/heads/master X-Git-Oldrev: 43dadcf3e7b0cba5a3ed3a8414b77e3fd75dfcd0 X-Git-Newrev: 8f921393e339090566c1589d81009caa954de90d Message-Id: <20211224161013.714BF3858C27@sourceware.org> Date: Fri, 24 Dec 2021 16:10:13 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 24 Dec 2021 16:10:13 -0000 https://gcc.gnu.org/g:8f921393e339090566c1589d81009caa954de90d commit r12-6113-g8f921393e339090566c1589d81009caa954de90d Author: Uros Bizjak Date: Fri Dec 24 17:09:36 2021 +0100 i386: Add V2SFmode DIV insn pattern [PR95046, PR103797] Use V4SFmode "DIVPS X,Y" with [y0, y1, 1.0f, 1.0f] as a divisor to avoid division by zero. 2021-12-24 Uroš Bizjak gcc/ChangeLog: PR target/95046 PR target/103797 * config/i386/mmx.md (divv2sf3): New instruction pattern. gcc/testsuite/ChangeLog: PR target/95046 PR target/103797 * gcc.target/i386/pr95046-1.c (test_div): Add. (dg-options): Add -mno-recip. Diff: --- gcc/config/i386/mmx.md | 20 ++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr95046-1.c | 11 ++++++++++- 2 files changed, 30 insertions(+), 1 deletion(-) diff --git a/gcc/config/i386/mmx.md b/gcc/config/i386/mmx.md index 6c5cbcfa52c..5a5755654c2 100644 --- a/gcc/config/i386/mmx.md +++ b/gcc/config/i386/mmx.md @@ -523,6 +523,26 @@ (set_attr "prefix" "*,orig,vex") (set_attr "mode" "V2SF,V4SF,V4SF")]) +(define_expand "divv2sf3" + [(set (match_operand:V2SF 0 "register_operand") + (div:V2SF (match_operand:V2SF 1 "register_operand") + (match_operand:V2SF 2 "register_operand")))] + "TARGET_MMX_WITH_SSE" +{ + rtx op0 = lowpart_subreg (V4SFmode, operands[0], + GET_MODE (operands[0])); + rtx op1 = lowpart_subreg (V4SFmode, operands[1], + GET_MODE (operands[1])); + rtx op2 = gen_rtx_VEC_CONCAT (V4SFmode, operands[2], + force_reg (V2SFmode, CONST1_RTX (V2SFmode))); + rtx tmp = gen_reg_rtx (V4SFmode); + + emit_insn (gen_rtx_SET (tmp, op2)); + + emit_insn (gen_divv4sf3 (op0, op1, tmp)); + DONE; +}) + (define_expand "mmx_v2sf3" [(set (match_operand:V2SF 0 "register_operand") (smaxmin:V2SF diff --git a/gcc/testsuite/gcc.target/i386/pr95046-1.c b/gcc/testsuite/gcc.target/i386/pr95046-1.c index bcc8bb5bfab..2a0e6db5fa5 100644 --- a/gcc/testsuite/gcc.target/i386/pr95046-1.c +++ b/gcc/testsuite/gcc.target/i386/pr95046-1.c @@ -1,6 +1,6 @@ /* PR target/95046 */ /* { dg-do compile { target { ! ia32 } } } */ -/* { dg-options "-O3 -ffast-math -msse2" } */ +/* { dg-options "-O3 -ffast-math -msse2 -mno-recip" } */ float r[2], a[2], b[2]; @@ -32,6 +32,15 @@ test_mult (void) /* { dg-final { scan-assembler "\tv?mulps" } } */ +void +test_div (void) +{ + for (int i = 0; i < 2; i++) + r[i] = a[i] / b[i]; +} + +/* { dg-final { scan-assembler "\tv?divps" } } */ + void test_min (void) {