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From: Roger Sayle <sayle@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-6341] nvptx: Add support for PTX's cnot instruction. Date: Fri, 7 Jan 2022 09:58:14 +0000 (GMT) [thread overview] Message-ID: <20220107095814.F125B3858D28@sourceware.org> (raw) https://gcc.gnu.org/g:659f8161f61d3f75c3a47cf646147e8f7b4dcb34 commit r12-6341-g659f8161f61d3f75c3a47cf646147e8f7b4dcb34 Author: Roger Sayle <roger@nextmovesoftware.com> Date: Fri Jan 7 09:57:21 2022 +0000 nvptx: Add support for PTX's cnot instruction. This is a simple patch, now that the nvptx backend has transitioned to STORE_FLAG_VALUE=1, that adds support for NVidia's cnot instruction, that implements C/C++ style logical negation. Previously, the simple function: int foo(int x) { return !x; } on nvptx-none with -O2 would generate: mov.u32 %r24, %ar0; setp.eq.u32 %r28, %r24, 0; selp.u32 %value, 1, 0, %r28; with this patch, GCC now generates: mov.u32 %r24, %ar0; cnot.b32 %value, %r24; 2022-01-07 Roger Sayle <roger@nextmovesoftware.com> gcc/ChangeLog * config/nvptx/nvptx.md (*cnot<mode>2): New define_insn. gcc/testsuite/ChangeLog * gcc.target/nvptx/cnot-1.c: New test case. Diff: --- gcc/config/nvptx/nvptx.md | 7 +++ gcc/testsuite/gcc.target/nvptx/cnot-1.c | 94 +++++++++++++++++++++++++++++++++ 2 files changed, 101 insertions(+) diff --git a/gcc/config/nvptx/nvptx.md b/gcc/config/nvptx/nvptx.md index a4c14a3f6c7..ce74672e5ae 100644 --- a/gcc/config/nvptx/nvptx.md +++ b/gcc/config/nvptx/nvptx.md @@ -592,6 +592,13 @@ "" "%.\\tnot.b%T0\\t%0, %1;") +(define_insn "*cnot<mode>2" + [(set (match_operand:HSDIM 0 "nvptx_register_operand" "=R") + (eq:HSDIM (match_operand:HSDIM 1 "nvptx_register_operand" "R") + (const_int 0)))] + "" + "%.\\tcnot.b%T0\\t%0, %1;") + (define_insn "bitrev<mode>2" [(set (match_operand:SDIM 0 "nvptx_register_operand" "=R") (unspec:SDIM [(match_operand:SDIM 1 "nvptx_register_operand" "R")] diff --git a/gcc/testsuite/gcc.target/nvptx/cnot-1.c b/gcc/testsuite/gcc.target/nvptx/cnot-1.c new file mode 100644 index 00000000000..d0bdccd2c47 --- /dev/null +++ b/gcc/testsuite/gcc.target/nvptx/cnot-1.c @@ -0,0 +1,94 @@ +/* { dg-do compile } */ +/* { dg-options "-O2" } */ + +int test1(int x) +{ + return !x; +} + +int test2(int x) +{ + return x ? 0 : 1; +} + +int test3(int x) +{ + return (x == 0) ? 1 : 0; +} + +unsigned int test4(unsigned int x) +{ + return !x; +} + +unsigned int test5(unsigned int x) +{ + return x ? 0 : 1; +} + +unsigned int test6(unsigned int x) +{ + return (x == 0) ? 1 : 0; +} + +short test7(short x) +{ + return !x; +} + +short test8(short x) +{ + return x ? 0 : 1; +} + +short test9(short x) +{ + return (x == 0) ? 1 : 0; +} + +unsigned short test10(unsigned short x) +{ + return !x; +} + +unsigned short test11(unsigned short x) +{ + return x ? 0 : 1; +} + +unsigned short test12(unsigned short x) +{ + return (x == 0) ? 1 : 0; +} + +long test13(long x) +{ + return !x; +} + +long test14(long x) +{ + return x ? 0 : 1; +} + +long test15(long x) +{ + return (x == 0) ? 1: 0; +} + +unsigned long test16(unsigned long x) +{ + return !x; +} + +unsigned long test17(unsigned long x) +{ + return x ? 0 : 1; +} + +unsigned long test18(unsigned long x) +{ + return (x == 0) ? 1 : 0; +} + +/* { dg-final { scan-assembler-times "cnot.b" 18 } } */
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