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From: hongtao Liu <liuhongt@gcc.gnu.org> To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-6538] Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask). Date: Thu, 13 Jan 2022 05:14:29 +0000 (GMT) [thread overview] Message-ID: <20220113051429.70B923858D39@sourceware.org> (raw) https://gcc.gnu.org/g:5f19303ada7db92c155332e7ba317233ca05946b commit r12-6538-g5f19303ada7db92c155332e7ba317233ca05946b Author: Haochen Jiang <haochen.jiang@intel.com> Date: Wed Jan 12 10:01:21 2022 +0800 Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask). From the perspective of the pipeline, `andn + and + ior` version take 2 cycles(AND and ANDN doesn't have dependence), but xor + and + xor will take 3 cycles. - xorl %edi, %esi andl %edx, %esi - movl %esi, %eax - xorl %edi, %eax + andn %edi, %edx, %eax + orl %esi, %eax gcc/ChangeLog: PR target/94790 * config/i386/i386.md (*xor2andn): New define_insn_and_split. gcc/testsuite/ChangeLog: PR target/94790 * gcc.target/i386/pr94790-1.c: New test. * gcc.target/i386/pr94790-2.c: Ditto. Diff: --- gcc/config/i386/i386.md | 38 +++++++++++++++++++++++++++++++ gcc/testsuite/gcc.target/i386/pr94790-1.c | 14 ++++++++++++ gcc/testsuite/gcc.target/i386/pr94790-2.c | 9 ++++++++ 3 files changed, 61 insertions(+) diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md index 376df1d51d1..9937643a273 100644 --- a/gcc/config/i386/i386.md +++ b/gcc/config/i386/i386.md @@ -10453,6 +10453,44 @@ (set_attr "znver1_decode" "double") (set_attr "mode" "DI")]) +;; PR target/94790: Optimize a ^ ((a ^ b) & mask) to (~mask & a) | (b & mask) +(define_insn_and_split "*xor2andn" + [(set (match_operand:SWI248 0 "nonimmediate_operand") + (xor:SWI248 + (and:SWI248 + (xor:SWI248 + (match_operand:SWI248 1 "nonimmediate_operand") + (match_operand:SWI248 2 "nonimmediate_operand")) + (match_operand:SWI248 3 "nonimmediate_operand")) + (match_dup 1))) + (clobber (reg:CC FLAGS_REG))] + "(TARGET_BMI || TARGET_AVX512BW) + && ix86_pre_reload_split ()" + "#" + "&& 1" + [(parallel [(set (match_dup 4) + (and:SWI248 + (not:SWI248 + (match_dup 3)) + (match_dup 1))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 5) + (and:SWI248 + (match_dup 2) + (match_dup 3))) + (clobber (reg:CC FLAGS_REG))]) + (parallel [(set (match_dup 0) + (ior:SWI248 + (match_dup 4) + (match_dup 5))) + (clobber (reg:CC FLAGS_REG))])] +{ + operands[1] = force_reg (<MODE>mode, operands[1]); + operands[3] = force_reg (<MODE>mode, operands[3]); + operands[4] = gen_reg_rtx (<MODE>mode); + operands[5] = gen_reg_rtx (<MODE>mode); +}) + ;; See comment for addsi_1_zext why we do use nonimmediate_operand (define_insn "*<code>si_1_zext" [(set (match_operand:DI 0 "register_operand" "=r") diff --git a/gcc/testsuite/gcc.target/i386/pr94790-1.c b/gcc/testsuite/gcc.target/i386/pr94790-1.c new file mode 100755 index 00000000000..1ff5fa25dfa --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr94790-1.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi" } */ +/* { dg-final { scan-assembler-times "andn\[ \\t\]" 2 } } */ +/* { dg-final { scan-assembler-not "xorl\[ \\t\]" } } */ + +unsigned r1(unsigned a, unsigned b, unsigned mask) +{ + return a ^ ((a ^ b) & mask); +} + +unsigned r2(unsigned a, unsigned b, unsigned mask) +{ + return (~mask & a) | (b & mask); +} diff --git a/gcc/testsuite/gcc.target/i386/pr94790-2.c b/gcc/testsuite/gcc.target/i386/pr94790-2.c new file mode 100755 index 00000000000..ad11d94e157 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr94790-2.c @@ -0,0 +1,9 @@ +/* { dg-do compile } */ +/* { dg-options "-O2 -mbmi" } */ +/* { dg-final { scan-assembler-not "andn\[ \\t\]" } } */ +/* { dg-final { scan-assembler-times "xorl\[ \\t\]" 2 } } */ + +unsigned r1(unsigned a, unsigned b, unsigned mask) +{ + return a ^ ((a ^ b) & mask) + (a ^ b); +}
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