[gcc r10-10398] rs6000: Add unspec wrapper to vsx_assemble_pair

[Peter Bergner <bergner@gcc.gnu.org>]

https://gcc.gnu.org/g:1221c37e515e69c6426994a4a77cb2651747c172

commit r10-10398-g1221c37e515e69c6426994a4a77cb2651747c172
Author: Peter Bergner <bergner@linux.ibm.com>
Date:   Fri Jan 14 21:41:03 2022 -0600

    rs6000: Add unspec wrapper to vsx_assemble_pair
    
    This backports the trunk handling of vsx_assemble_pair with a unspec
    wrapper and splits it late (split2).
    
    2022-01-14  Peter Bergner  <bergner@linux.ibm.com>
    
    gcc/
            * config/rs6000/mma.md (UNSPEC_VSX_ASSEMBLE): New unspec.
            (vsx_assemble_pair): Use mma_assemble_input_operand.
            Expand into UNSPEC_VSX_ASSEMBLE wrapper.
            (*vsx_assemble_pair): New define_insn_and_split.
            * config/rs6000/rs6000.c (rs6000_split_multireg_move): Handle
            UNSPEC_VSX_ASSEMBLE.

Diff:
---
 gcc/config/rs6000/mma.md   | 35 ++++++++++++++++++++++++-----------
 gcc/config/rs6000/rs6000.c | 14 ++++++++++----
 2 files changed, 34 insertions(+), 15 deletions(-)

diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index f39a5c8ba99..c267a4c82e2 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -36,7 +36,8 @@
 ;; Constants for creating unspecs
 
 (define_c_enum "unspec"
-  [UNSPEC_MMA_ASSEMBLE_ACC
+  [UNSPEC_VSX_ASSEMBLE
+   UNSPEC_MMA_ASSEMBLE_ACC
    UNSPEC_MMA_PMXVBF16GER2
    UNSPEC_MMA_PMXVBF16GER2NN
    UNSPEC_MMA_PMXVBF16GER2NP
@@ -350,19 +351,31 @@
 
 (define_expand "vsx_assemble_pair"
   [(match_operand:POI 0 "vsx_register_operand")
-   (match_operand:V16QI 1 "input_operand")
-   (match_operand:V16QI 2 "input_operand")]
+   (match_operand:V16QI 1 "mma_assemble_input_operand")
+   (match_operand:V16QI 2 "mma_assemble_input_operand")]
   "TARGET_MMA"
 {
-  rtx dst;
-
-  /* Let the compiler know the code below fully defines our output value.  */
-  emit_clobber (operands[0]);
+  rtx src = gen_rtx_UNSPEC (POImode,
+                            gen_rtvec (2, operands[1], operands[2]),
+                            UNSPEC_VSX_ASSEMBLE);
+  emit_move_insn (operands[0], src);
+  DONE;
+})
 
-  dst = simplify_gen_subreg (V16QImode, operands[0], POImode, 0);
-  emit_move_insn (dst, operands[1]);
-  dst = simplify_gen_subreg (V16QImode, operands[0], POImode, 16);
-  emit_move_insn (dst, operands[2]);
+(define_insn_and_split "*vsx_assemble_pair"
+  [(set (match_operand:POI 0 "vsx_register_operand" "=wa")
+        (unspec:POI [(match_operand:V16QI 1 "mma_assemble_input_operand" "mwa")
+		     (match_operand:V16QI 2 "mma_assemble_input_operand" "mwa")]
+                     UNSPEC_VSX_ASSEMBLE))]
+  "TARGET_MMA"
+  "#"
+  "&& reload_completed"
+  [(const_int 0)]
+{
+  rtx src = gen_rtx_UNSPEC (POImode,
+                            gen_rtvec (2, operands[1], operands[2]),
+                            UNSPEC_VSX_ASSEMBLE);
+  rs6000_split_multireg_move (operands[0], src);
   DONE;
 })
 
diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index a9d1769350e..4b473e00be3 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -16018,9 +16018,13 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 
       if (GET_CODE (src) == UNSPEC)
 	{
-	  gcc_assert (REG_P (dst)
-		      && FP_REGNO_P (REGNO (dst))
-		      && XINT (src, 1) == UNSPEC_MMA_ASSEMBLE_ACC);
+	  gcc_assert (XINT (src, 1) == UNSPEC_VSX_ASSEMBLE
+		      || XINT (src, 1) == UNSPEC_MMA_ASSEMBLE_ACC);
+          gcc_assert (REG_P (dst));
+          if (GET_MODE (src) == PXImode)
+            gcc_assert (FP_REGNO_P (REGNO (dst)));
+          if (GET_MODE (src) == POImode)
+            gcc_assert (VSX_REGNO_P (REGNO (dst)));
 
 	  reg_mode = GET_MODE (XVECEXP (src, 0, 0));
 	  int nvecs = XVECLEN (src, 0);
@@ -16033,7 +16037,9 @@ rs6000_split_multireg_move (rtx dst, rtx src)
 
 	  /* We are writing an accumulator register, so we have to
 	     prime it after we've written it.  */
-	  emit_insn (gen_mma_xxmtacc (dst, dst));
+	  if (TARGET_MMA
+	      && GET_MODE (dst) == PXImode && FP_REGNO_P (REGNO (dst)))
+	    emit_insn (gen_mma_xxmtacc (dst, dst));
 
 	  return;
 	}