[gcc r12-6620] rs6000: Split pattern for TI to V1TI move [PR103124]

[HaoChen Gui <guihaoc@gcc.gnu.org>]

https://gcc.gnu.org/g:240dd6c063b481c092c9ec406b69b400f6f033f1

commit r12-6620-g240dd6c063b481c092c9ec406b69b400f6f033f1
Author: Haochen Gui <guihaoc@gcc.gnu.org>
Date:   Mon Jan 17 11:24:20 2022 +0800

    rs6000: Split pattern for TI to V1TI move [PR103124]
    
    This patch defines a new split pattern for TI to V1TI move.  The pattern concatenates two subreg:DI of a TI to a V2DI.  With the pattern, the subreg pass can do register split for TI when there is a TI to V1TI move.
    
    gcc/
    
            PR target/103124
            * config/rs6000/vsx.md (split pattern for TI to V1TI move): Defined.
    
    gcc/testsuite/
    
            PR target/103124
            * gcc.target/powerpc/pr103124.c: New testcase.

Diff:
---
 gcc/config/rs6000/vsx.md                    | 16 ++++++++++++++++
 gcc/testsuite/gcc.target/powerpc/pr103124.c | 12 ++++++++++++
 2 files changed, 28 insertions(+)

diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index 7bcf48fa0b0..65bbc763eb0 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -6586,3 +6586,19 @@
    [(set_attr "type" "vecperm")
     (set_attr "prefixed" "yes")])
 
+;; Construct V1TI by vsx_concat_v2di
+(define_split
+  [(set (match_operand:V1TI 0 "vsx_register_operand")
+	(subreg:V1TI
+	  (match_operand:TI 1 "int_reg_operand") 0 ))]
+  "TARGET_P9_VECTOR && !reload_completed"
+  [(const_int 0)]
+{
+  rtx tmp1 = simplify_gen_subreg (DImode, operands[1], TImode, 0);
+  rtx tmp2 = simplify_gen_subreg (DImode, operands[1], TImode, 8);
+  rtx tmp3 = gen_reg_rtx (V2DImode);
+  emit_insn (gen_vsx_concat_v2di (tmp3, tmp1, tmp2));
+  rtx tmp4 = simplify_gen_subreg (V1TImode, tmp3, V2DImode, 0);
+  emit_move_insn (operands[0], tmp4);
+  DONE;
+})
diff --git a/gcc/testsuite/gcc.target/powerpc/pr103124.c b/gcc/testsuite/gcc.target/powerpc/pr103124.c
new file mode 100644
index 00000000000..dc7bb9c91d4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/pr103124.c
@@ -0,0 +1,12 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-require-effective-target int128 } */
+/* { dg-options "-O2 -mdejagnu-cpu=power9" } */
+/* { dg-final { scan-assembler-not {\mmr\M} } } */
+
+vector __int128 add (long long a)
+{
+  vector __int128 b;
+  b = (vector __int128) {a};
+  return b;
+}