From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: by sourceware.org (Postfix, from userid 2153) id 1E0F83858032; Wed, 19 Jan 2022 01:25:13 +0000 (GMT) DKIM-Filter: OpenDKIM Filter v2.11.0 sourceware.org 1E0F83858032 MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="utf-8" From: Jakub Jelinek To: gcc-cvs@gcc.gnu.org Subject: [gcc r12-6715] i386: Fix GLC tuning with -masm=intel [PR104104] X-Act-Checkin: gcc X-Git-Author: Jakub Jelinek X-Git-Refname: refs/heads/master X-Git-Oldrev: 6325041c2b68af096195e0eef92091b2e293e950 X-Git-Newrev: ddce00dba244d889d688490517fb106169a72f01 Message-Id: <20220119012513.1E0F83858032@sourceware.org> Date: Wed, 19 Jan 2022 01:25:13 +0000 (GMT) X-BeenThere: gcc-cvs@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-cvs mailing list List-Unsubscribe: , List-Archive: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 19 Jan 2022 01:25:13 -0000 https://gcc.gnu.org/g:ddce00dba244d889d688490517fb106169a72f01 commit r12-6715-gddce00dba244d889d688490517fb106169a72f01 Author: Jakub Jelinek Date: Wed Jan 19 02:24:06 2022 +0100 i386: Fix GLC tuning with -masm=intel [PR104104] > > On Sat, Jan 15, 2022 at 5:39 PM Hongyu Wang wrote: > > > Thanks for the suggestion, here is the updated patch that survived > > > bootstrap/regtest. Unfortunately the patch results in assembler failures with -masm=intel. > > > > + if (TARGET_DEST_FALSE_DEPENDENCY > > > > + && get_attr_dest_false_dep (insn) == > > > > + DEST_FALSE_DEP_TRUE) > > > > + output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); All the vxorps insns were emitted like the above, which means for -masm=sysv it looks like vxorps %xmm3, %xmm3, %xmm3 but for -masm=intel like: vxorps We want obviously vxorps xmm3, xmm3, xmm3 so the following patch just drops the errorneous {}s. 2022-01-19 Jakub Jelinek PR target/104104 * config/i386/sse.md (__, avx512fp16_sh_v8hf, avx512dq_mul3, _permvar, avx2_perm_1, avx512f_perm_1, avx512dq_rangep, avx512dq_ranges, _getmant, avx512f_vgetmant): Use vxorps\t%x0, %x0, %x0 instead of vxorps\t{%x0, %x0, %x0}. * gcc.target/i386/pr104104.c: New test. Diff: --- gcc/config/i386/sse.md | 20 ++++++++++---------- gcc/testsuite/gcc.target/i386/pr104104.c | 10 ++++++++++ 2 files changed, 20 insertions(+), 10 deletions(-) diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 34175fd5258..829107e00c9 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -6539,7 +6539,7 @@ { if (TARGET_DEST_FALSE_DEP_FOR_GLC && ) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "v\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "ssemul") @@ -6750,7 +6750,7 @@ { if (TARGET_DEST_FALSE_DEP_FOR_GLC && ) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vsh\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "ssemul") @@ -15222,7 +15222,7 @@ && && !reg_mentioned_p (operands[0], operands[1]) && !reg_mentioned_p (operands[0], operands[2])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vpmullq\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "sseimul") @@ -24658,7 +24658,7 @@ && && !reg_mentioned_p (operands[0], operands[1]) && !reg_mentioned_p (operands[0], operands[2])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vperm\t{%1, %2, %0|%0, %2, %1}"; } [(set_attr "type" "sselog") @@ -24900,7 +24900,7 @@ if (TARGET_DEST_FALSE_DEP_FOR_GLC && && !reg_mentioned_p (operands[0], operands[1])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vperm\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "sselog") @@ -24975,7 +24975,7 @@ if (TARGET_DEST_FALSE_DEP_FOR_GLC && && !reg_mentioned_p (operands[0], operands[1])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vperm\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "type" "sselog") @@ -26880,7 +26880,7 @@ && && !reg_mentioned_p (operands[0], operands[1]) && !reg_mentioned_p (operands[0], operands[2])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vrange\t{%3, %2, %1, %0|%0, %1, %2, %3}"; } [(set_attr "type" "sse") @@ -26903,7 +26903,7 @@ && && !reg_mentioned_p (operands[0], operands[1]) && !reg_mentioned_p (operands[0], operands[2])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vrange\t{%3, %2, %1, %0|%0, %1, %2, %3}"; } [(set_attr "type" "sse") @@ -26949,7 +26949,7 @@ if (TARGET_DEST_FALSE_DEP_FOR_GLC && && MEM_P (operands[1])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vgetmant\t{%2, %1, %0|%0, %1, %2}"; } [(set_attr "prefix" "evex") @@ -26971,7 +26971,7 @@ && && !reg_mentioned_p (operands[0], operands[1]) && !reg_mentioned_p (operands[0], operands[2])) - output_asm_insn ("vxorps\t{%x0, %x0, %x0}", operands); + output_asm_insn ("vxorps\t%x0, %x0, %x0", operands); return "vgetmant\t{%3, %2, %1, %0|%0, %1, %2, %3}"; } [(set_attr "prefix" "evex") diff --git a/gcc/testsuite/gcc.target/i386/pr104104.c b/gcc/testsuite/gcc.target/i386/pr104104.c new file mode 100644 index 00000000000..1653caedc03 --- /dev/null +++ b/gcc/testsuite/gcc.target/i386/pr104104.c @@ -0,0 +1,10 @@ +/* PR target/104104 */ +/* { dg-do assemble { target vect_simd_clones } } */ +/* { dg-require-effective-target masm_intel } */ +/* { dg-options "-march=alderlake -masm=intel -O1 -fallow-store-data-races -funroll-all-loops" } */ + +__attribute__ ((simd)) short int +foo (void) +{ + return 0; +}